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authorDavid Goodwin <david_goodwin@apple.com>2009-07-08 16:09:28 +0000
committerDavid Goodwin <david_goodwin@apple.com>2009-07-08 16:09:28 +0000
commit334c26473bba3ad8b88341bb0d25d0ac2008bb8d (patch)
tree04d6f19211a1608488c595de5d573f70b9a6388e /lib/Target/ARM/Thumb1InstrInfo.h
parent8c899ee031481dbece5f111379a274c848cb5902 (diff)
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Checkpoint Thumb2 Instr info work. Generalized base code so that it can be shared between ARM and Thumb2. Not yet activated because register information must be generalized first.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75010 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/ARM/Thumb1InstrInfo.h')
-rw-r--r--lib/Target/ARM/Thumb1InstrInfo.h10
1 files changed, 10 insertions, 0 deletions
diff --git a/lib/Target/ARM/Thumb1InstrInfo.h b/lib/Target/ARM/Thumb1InstrInfo.h
index 1bfa1d0bdc..67b78fbedf 100644
--- a/lib/Target/ARM/Thumb1InstrInfo.h
+++ b/lib/Target/ARM/Thumb1InstrInfo.h
@@ -27,6 +27,16 @@ class Thumb1InstrInfo : public ARMBaseInstrInfo {
public:
explicit Thumb1InstrInfo(const ARMSubtarget &STI);
+ // Return the non-pre/post incrementing version of 'Opc'. Return 0
+ // if there is not such an opcode.
+ unsigned getUnindexedOpcode(unsigned Opc) const;
+
+ // Return the opcode that implements 'Op', or 0 if no opcode
+ unsigned getOpcode(ARMII::Op Op) const;
+
+ // Return true if the block does not fall through.
+ bool BlockHasNoFallThrough(const MachineBasicBlock &MBB) const;
+
/// getRegisterInfo - TargetInstrInfo is a superset of MRegister info. As
/// such, whenever a client has an instance of instruction info, it should
/// always be able to get register info as well (through this method).