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| author | Dale Johannesen <dalej@apple.com> | 2010-06-15 22:08:33 +0000 |
|---|---|---|
| committer | Dale Johannesen <dalej@apple.com> | 2010-06-15 22:08:33 +0000 |
| commit | 6470a116f17b70aba0c2e7ee751551a5ac9797f6 (patch) | |
| tree | eee212d8e4b620fda7d40823a1198c025f0b3dd8 /lib/Target/ARM/Thumb2InstrInfo.cpp | |
| parent | 8a3eab9b20acb7193285bc31c9a3e23c7c7d7173 (diff) | |
| download | llvm-6470a116f17b70aba0c2e7ee751551a5ac9797f6.tar.gz llvm-6470a116f17b70aba0c2e7ee751551a5ac9797f6.tar.bz2 llvm-6470a116f17b70aba0c2e7ee751551a5ac9797f6.tar.xz | |
Next round of tail call changes. Register used in a tail
call must not be callee-saved; following x86, add a new
regclass to represent this. Also fixes a couple of bugs.
Still disabled by default; Thumb doesn't work yet.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106053 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/ARM/Thumb2InstrInfo.cpp')
| -rw-r--r-- | lib/Target/ARM/Thumb2InstrInfo.cpp | 12 |
1 files changed, 7 insertions, 5 deletions
diff --git a/lib/Target/ARM/Thumb2InstrInfo.cpp b/lib/Target/ARM/Thumb2InstrInfo.cpp index 8c19b9f5a6..f78111f7b9 100644 --- a/lib/Target/ARM/Thumb2InstrInfo.cpp +++ b/lib/Target/ARM/Thumb2InstrInfo.cpp @@ -42,8 +42,8 @@ Thumb2InstrInfo::copyRegToReg(MachineBasicBlock &MBB, const TargetRegisterClass *DestRC, const TargetRegisterClass *SrcRC, DebugLoc DL) const { - if (DestRC == ARM::GPRRegisterClass) { - if (SrcRC == ARM::GPRRegisterClass) { + if (DestRC == ARM::GPRRegisterClass || DestRC == ARM::tcGPRRegisterClass) { + if (SrcRC == ARM::GPRRegisterClass || SrcRC == ARM::tcGPRRegisterClass) { BuildMI(MBB, I, DL, get(ARM::tMOVgpr2gpr), DestReg).addReg(SrcReg); return true; } else if (SrcRC == ARM::tGPRRegisterClass) { @@ -51,7 +51,7 @@ Thumb2InstrInfo::copyRegToReg(MachineBasicBlock &MBB, return true; } } else if (DestRC == ARM::tGPRRegisterClass) { - if (SrcRC == ARM::GPRRegisterClass) { + if (SrcRC == ARM::GPRRegisterClass || SrcRC == ARM::tcGPRRegisterClass) { BuildMI(MBB, I, DL, get(ARM::tMOVgpr2tgpr), DestReg).addReg(SrcReg); return true; } else if (SrcRC == ARM::tGPRRegisterClass) { @@ -70,7 +70,8 @@ storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, unsigned SrcReg, bool isKill, int FI, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const { - if (RC == ARM::GPRRegisterClass || RC == ARM::tGPRRegisterClass) { + if (RC == ARM::GPRRegisterClass || RC == ARM::tGPRRegisterClass || + RC == ARM::tcGPRRegisterClass) { DebugLoc DL; if (I != MBB.end()) DL = I->getDebugLoc(); @@ -95,7 +96,8 @@ loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, unsigned DestReg, int FI, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const { - if (RC == ARM::GPRRegisterClass || RC == ARM::tGPRRegisterClass) { + if (RC == ARM::GPRRegisterClass || RC == ARM::tGPRRegisterClass || + RC == ARM::tcGPRRegisterClass) { DebugLoc DL; if (I != MBB.end()) DL = I->getDebugLoc(); |