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| author | Tilmann Scheller <tilmann.scheller@googlemail.com> | 2013-09-05 11:59:43 +0000 |
|---|---|---|
| committer | Tilmann Scheller <tilmann.scheller@googlemail.com> | 2013-09-05 11:59:43 +0000 |
| commit | 8f3d54d057007552d0abc37c87a50ef34a7ab9ef (patch) | |
| tree | 640d07133c8f2ab9f909e7b2c464f96e6c1a5496 /lib/Target/ARM/Thumb2InstrInfo.cpp | |
| parent | 10b5086e6e945b830ff909821240eff5c4a42bfc (diff) | |
| download | llvm-8f3d54d057007552d0abc37c87a50ef34a7ab9ef.tar.gz llvm-8f3d54d057007552d0abc37c87a50ef34a7ab9ef.tar.bz2 llvm-8f3d54d057007552d0abc37c87a50ef34a7ab9ef.tar.xz | |
Reverting 190043 for now.
Solution is not sufficient to prevent 'mov pc, lr' being emitted for jump table code.
Test case doesn't trigger the added functionality.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190047 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/ARM/Thumb2InstrInfo.cpp')
| -rw-r--r-- | lib/Target/ARM/Thumb2InstrInfo.cpp | 16 |
1 files changed, 2 insertions, 14 deletions
diff --git a/lib/Target/ARM/Thumb2InstrInfo.cpp b/lib/Target/ARM/Thumb2InstrInfo.cpp index 7c51c70f67..286eaa0946 100644 --- a/lib/Target/ARM/Thumb2InstrInfo.cpp +++ b/lib/Target/ARM/Thumb2InstrInfo.cpp @@ -152,13 +152,7 @@ storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, // gsub_0, but needs an extra constraint for gsub_1 (which could be sp // otherwise). MachineRegisterInfo *MRI = &MF.getRegInfo(); - const TargetRegisterClass* TargetClass = TRI->getMatchingSuperRegClass(RC, - &ARM::rGPRRegClass, - ARM::gsub_1); - assert(TargetClass && "No Matching GPRPair with gsub_1 in rGPRRegClass"); - const TargetRegisterClass* ConstrainedClass = - MRI->constrainRegClass(SrcReg, TargetClass); - assert(ConstrainedClass && "Couldn't constrain the register class"); + MRI->constrainRegClass(SrcReg, &ARM::GPRPair_with_gsub_1_in_rGPRRegClass); MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(ARM::t2STRDi8)); AddDReg(MIB, SrcReg, ARM::gsub_0, getKillRegState(isKill), TRI); @@ -199,13 +193,7 @@ loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, // gsub_0, but needs an extra constraint for gsub_1 (which could be sp // otherwise). MachineRegisterInfo *MRI = &MF.getRegInfo(); - const TargetRegisterClass* TargetClass = TRI->getMatchingSuperRegClass(RC, - &ARM::rGPRRegClass, - ARM::gsub_1); - assert(TargetClass && "No Matching GPRPair with gsub_1 in rGPRRegClass"); - const TargetRegisterClass* ConstrainedClass = - MRI->constrainRegClass(DestReg, TargetClass); - assert(ConstrainedClass && "Couldn't constrain the register class"); + MRI->constrainRegClass(DestReg, &ARM::GPRPair_with_gsub_1_in_rGPRRegClass); MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(ARM::t2LDRDi8)); AddDReg(MIB, DestReg, ARM::gsub_0, RegState::DefineNoRead, TRI); |