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| author | David Goodwin <david_goodwin@apple.com> | 2009-07-08 20:28:28 +0000 |
|---|---|---|
| committer | David Goodwin <david_goodwin@apple.com> | 2009-07-08 20:28:28 +0000 |
| commit | 77521f5232e679aa3de10aaaed2464aa91d7ff55 (patch) | |
| tree | 2a79a341e79ee5621555a0f72098c430063364cf /lib/Target/ARM/Thumb2RegisterInfo.cpp | |
| parent | cecbc964e1996c39881b3442fc7390e82050f527 (diff) | |
| download | llvm-77521f5232e679aa3de10aaaed2464aa91d7ff55.tar.gz llvm-77521f5232e679aa3de10aaaed2464aa91d7ff55.tar.bz2 llvm-77521f5232e679aa3de10aaaed2464aa91d7ff55.tar.xz | |
Generalize opcode selection in ARMBaseRegisterInfo.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75036 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/ARM/Thumb2RegisterInfo.cpp')
| -rw-r--r-- | lib/Target/ARM/Thumb2RegisterInfo.cpp | 13 |
1 files changed, 7 insertions, 6 deletions
diff --git a/lib/Target/ARM/Thumb2RegisterInfo.cpp b/lib/Target/ARM/Thumb2RegisterInfo.cpp index c1326e60e1..bca205a039 100644 --- a/lib/Target/ARM/Thumb2RegisterInfo.cpp +++ b/lib/Target/ARM/Thumb2RegisterInfo.cpp @@ -13,6 +13,7 @@ #include "ARM.h" #include "ARMAddressingModes.h" +#include "ARMBaseInstrInfo.h" #include "ARMMachineFunctionInfo.h" #include "ARMSubtarget.h" #include "Thumb2InstrInfo.h" @@ -47,7 +48,7 @@ Thumb2RegisterInfo::Thumb2RegisterInfo(const ARMBaseInstrInfo &tii, /// specified immediate. void Thumb2RegisterInfo::emitLoadConstPool(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI, - const TargetInstrInfo *TII, DebugLoc dl, + DebugLoc dl, unsigned DestReg, int Val, ARMCC::CondCodes Pred, unsigned PredReg) const { @@ -56,8 +57,8 @@ void Thumb2RegisterInfo::emitLoadConstPool(MachineBasicBlock &MBB, Constant *C = ConstantInt::get(Type::Int32Ty, Val); unsigned Idx = ConstantPool->getConstantPoolIndex(C, 4); - BuildMI(MBB, MBBI, dl, TII->get(ARM::tLDRcp), DestReg) - .addConstantPoolIndex(Idx); + BuildMI(MBB, MBBI, dl, TII.get(ARM::t2LDRpci), DestReg) + .addConstantPoolIndex(Idx).addImm(Pred).addReg(PredReg); } const TargetRegisterClass* @@ -131,7 +132,7 @@ void emitThumbRegPlusImmInReg(MachineBasicBlock &MBB, BuildMI(MBB, MBBI, dl, TII.get(ARM::tNEG), LdReg) .addReg(LdReg, RegState::Kill); } else - MRI.emitLoadConstPool(MBB, MBBI, &TII, dl, LdReg, NumBytes); + MRI.emitLoadConstPool(MBB, MBBI, dl, LdReg, NumBytes); // Emit add / sub. int Opc = (isSub) ? ARM::tSUBrr : (isHigh ? ARM::tADDhirr : ARM::tADDrr); @@ -505,7 +506,7 @@ void Thumb2RegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II, emitThumbRegPlusImmInReg(MBB, II, TmpReg, FrameReg, Offset, false, TII, *this, dl); else { - emitLoadConstPool(MBB, II, &TII, dl, TmpReg, Offset); + emitLoadConstPool(MBB, II, dl, TmpReg, Offset); UseRR = true; } } else @@ -543,7 +544,7 @@ void Thumb2RegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II, emitThumbRegPlusImmInReg(MBB, II, TmpReg, FrameReg, Offset, false, TII, *this, dl); else { - emitLoadConstPool(MBB, II, &TII, dl, TmpReg, Offset); + emitLoadConstPool(MBB, II, dl, TmpReg, Offset); UseRR = true; } } else |