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authorBill Wendling <isanbard@gmail.com>2013-06-07 05:54:19 +0000
committerBill Wendling <isanbard@gmail.com>2013-06-07 05:54:19 +0000
commit57148c166ab232191098492633c924fad9c44ef3 (patch)
tree2742791240f5d1a8babb627efc05493190cadb28 /lib/Target/ARM/Thumb2RegisterInfo.h
parent4393f48c03300203594e22d248808f20dd59d886 (diff)
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Don't cache the instruction and register info from the TargetMachine, because
the internals of TargetMachine could change. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183488 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/ARM/Thumb2RegisterInfo.h')
-rw-r--r--lib/Target/ARM/Thumb2RegisterInfo.h6
1 files changed, 3 insertions, 3 deletions
diff --git a/lib/Target/ARM/Thumb2RegisterInfo.h b/lib/Target/ARM/Thumb2RegisterInfo.h
index 6b397e8696..b1d63fa86d 100644
--- a/lib/Target/ARM/Thumb2RegisterInfo.h
+++ b/lib/Target/ARM/Thumb2RegisterInfo.h
@@ -20,12 +20,12 @@
#include "llvm/Target/TargetRegisterInfo.h"
namespace llvm {
- class ARMSubtarget;
- class ARMBaseInstrInfo;
+
+class ARMSubtarget;
struct Thumb2RegisterInfo : public ARMBaseRegisterInfo {
public:
- Thumb2RegisterInfo(const ARMBaseInstrInfo &tii, const ARMSubtarget &STI);
+ Thumb2RegisterInfo(const ARMSubtarget &STI);
/// emitLoadConstPool - Emits a load from constpool to materialize the
/// specified immediate.