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author | Chad Rosier <mcrosier@codeaurora.org> | 2014-04-28 16:21:50 +0000 |
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committer | Chad Rosier <mcrosier@codeaurora.org> | 2014-04-28 16:21:50 +0000 |
commit | 2f3691eb61b7d77e21895fcacdb0fa6553ec99ec (patch) | |
tree | 434d338d3b4d7522d02ddb48861683fda3deb9b9 /lib/Target/ARM64/ARM64AdvSIMDScalarPass.cpp | |
parent | bb626f0ed941f0caaa4e718e678e08ecc52fe2e0 (diff) | |
download | llvm-2f3691eb61b7d77e21895fcacdb0fa6553ec99ec.tar.gz llvm-2f3691eb61b7d77e21895fcacdb0fa6553ec99ec.tar.bz2 llvm-2f3691eb61b7d77e21895fcacdb0fa6553ec99ec.tar.xz |
[ARM64] Fix an issue where we were always assuming a copy was coming from a D subregister.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207423 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/ARM64/ARM64AdvSIMDScalarPass.cpp')
-rw-r--r-- | lib/Target/ARM64/ARM64AdvSIMDScalarPass.cpp | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/lib/Target/ARM64/ARM64AdvSIMDScalarPass.cpp b/lib/Target/ARM64/ARM64AdvSIMDScalarPass.cpp index 851572485d..87eec8f616 100644 --- a/lib/Target/ARM64/ARM64AdvSIMDScalarPass.cpp +++ b/lib/Target/ARM64/ARM64AdvSIMDScalarPass.cpp @@ -90,7 +90,7 @@ public: virtual bool runOnMachineFunction(MachineFunction &F); const char *getPassName() const { - return "AdvSIMD scalar operation optimization"; + return "AdvSIMD Scalar Operation Optimization"; } virtual void getAnalysisUsage(AnalysisUsage &AU) const { @@ -117,7 +117,7 @@ static bool isFPR64(unsigned Reg, unsigned SubReg, SubReg == 0) || (MRI->getRegClass(Reg)->hasSuperClassEq(&ARM64::FPR128RegClass) && SubReg == ARM64::dsub); - // Physical register references just check the regist class directly. + // Physical register references just check the register class directly. return (ARM64::FPR64RegClass.contains(Reg) && SubReg == 0) || (ARM64::FPR128RegClass.contains(Reg) && SubReg == ARM64::dsub); } @@ -148,7 +148,7 @@ static unsigned getSrcFromCopy(const MachineInstr *MI, MRI) && isFPR64(MI->getOperand(1).getReg(), MI->getOperand(1).getSubReg(), MRI)) { - SubReg = ARM64::dsub; + SubReg = MI->getOperand(1).getSubReg(); return MI->getOperand(1).getReg(); } } |