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author | Renato Golin <renato.golin@linaro.org> | 2014-05-06 16:51:25 +0000 |
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committer | Renato Golin <renato.golin@linaro.org> | 2014-05-06 16:51:25 +0000 |
commit | 22f779d1fd0d7a7e878a3c28bc5d9910ae655df3 (patch) | |
tree | 272b3978eb4e467ad4854aa00a03dda055046001 /lib/Target/ARM | |
parent | b8894488415a81bb6bdaf9851acacc93a4e7cfe2 (diff) | |
download | llvm-22f779d1fd0d7a7e878a3c28bc5d9910ae655df3.tar.gz llvm-22f779d1fd0d7a7e878a3c28bc5d9910ae655df3.tar.bz2 llvm-22f779d1fd0d7a7e878a3c28bc5d9910ae655df3.tar.xz |
Implememting named register intrinsics
This patch implements the infrastructure to use named register constructs in
programs that need access to specific registers (bare metal, kernels, etc).
So far, only the stack pointer is supported as a technology preview, but as it
is, the intrinsic can already support all non-allocatable registers from any
architecture.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208104 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/ARM')
-rw-r--r-- | lib/Target/ARM/ARMISelLowering.cpp | 11 | ||||
-rw-r--r-- | lib/Target/ARM/ARMISelLowering.h | 2 |
2 files changed, 13 insertions, 0 deletions
diff --git a/lib/Target/ARM/ARMISelLowering.cpp b/lib/Target/ARM/ARMISelLowering.cpp index e1e403c6e7..a8f0d8cc0f 100644 --- a/lib/Target/ARM/ARMISelLowering.cpp +++ b/lib/Target/ARM/ARMISelLowering.cpp @@ -3784,6 +3784,17 @@ SDValue ARMTargetLowering::LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const { return FrameAddr; } +// FIXME? Maybe this could be a TableGen attribute on some registers and +// this table could be generated automatically from RegInfo. +unsigned ARMTargetLowering::getRegisterByName(const char* RegName) const { + unsigned Reg = StringSwitch<unsigned>(RegName) + .Case("sp", ARM::SP) + .Default(0); + if (Reg) + return Reg; + report_fatal_error("Invalid register name global variable"); +} + /// ExpandBITCAST - If the target supports VFP, this function is called to /// expand a bit convert where either the source or destination type is i64 to /// use a VMOVDRR or VMOVRRD node. This should not be done when the non-i64 diff --git a/lib/Target/ARM/ARMISelLowering.h b/lib/Target/ARM/ARMISelLowering.h index e8dd043ecd..7f28a251f5 100644 --- a/lib/Target/ARM/ARMISelLowering.h +++ b/lib/Target/ARM/ARMISelLowering.h @@ -461,6 +461,8 @@ namespace llvm { SDValue LowerFSINCOS(SDValue Op, SelectionDAG &DAG) const; SDValue LowerDivRem(SDValue Op, SelectionDAG &DAG) const; + unsigned getRegisterByName(const char* RegName) const; + /// isFMAFasterThanFMulAndFAdd - Return true if an FMA operation is faster /// than a pair of fmul and fadd instructions. fmuladd intrinsics will be /// expanded to FMAs when this method returns true, otherwise fmuladd is |