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author | Bill Wendling <isanbard@gmail.com> | 2011-03-07 23:38:41 +0000 |
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committer | Bill Wendling <isanbard@gmail.com> | 2011-03-07 23:38:41 +0000 |
commit | 3116dce33840a115130c5f8ffcb9679d023496d6 (patch) | |
tree | 5785ba082080308e283bebd9de4006abfd756360 /lib/Target/ARM | |
parent | 0d8ccaa5c8db820b5b93f37e51563148c57ba6b8 (diff) | |
download | llvm-3116dce33840a115130c5f8ffcb9679d023496d6.tar.gz llvm-3116dce33840a115130c5f8ffcb9679d023496d6.tar.bz2 llvm-3116dce33840a115130c5f8ffcb9679d023496d6.tar.xz |
Rename the narrow shift right immediate operands to "shr_imm*" operands. Also
expand the testing of the narrowing shift right instructions.
No functionality change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127193 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/ARM')
-rw-r--r-- | lib/Target/ARM/ARMCodeEmitter.cpp | 8 | ||||
-rw-r--r-- | lib/Target/ARM/ARMInstrFormats.td | 31 | ||||
-rw-r--r-- | lib/Target/ARM/ARMInstrNEON.td | 6 | ||||
-rw-r--r-- | lib/Target/ARM/ARMMCCodeEmitter.cpp | 32 |
4 files changed, 46 insertions, 31 deletions
diff --git a/lib/Target/ARM/ARMCodeEmitter.cpp b/lib/Target/ARM/ARMCodeEmitter.cpp index 853f234f8c..fa7371626f 100644 --- a/lib/Target/ARM/ARMCodeEmitter.cpp +++ b/lib/Target/ARM/ARMCodeEmitter.cpp @@ -312,11 +312,13 @@ namespace { unsigned getRegisterListOpValue(const MachineInstr &MI, unsigned Op) const { return 0; } - unsigned getNarrowShiftRight16Imm(const MachineInstr &MI, unsigned Op) + unsigned getShiftRight8Imm(const MachineInstr &MI, unsigned Op) const { return 0; } - unsigned getNarrowShiftRight32Imm(const MachineInstr &MI, unsigned Op) + unsigned getShiftRight16Imm(const MachineInstr &MI, unsigned Op) const { return 0; } - unsigned getNarrowShiftRight64Imm(const MachineInstr &MI, unsigned Op) + unsigned getShiftRight32Imm(const MachineInstr &MI, unsigned Op) + const { return 0; } + unsigned getShiftRight64Imm(const MachineInstr &MI, unsigned Op) const { return 0; } /// getMovi32Value - Return binary encoding of operand for movw/movt. If the diff --git a/lib/Target/ARM/ARMInstrFormats.td b/lib/Target/ARM/ARMInstrFormats.td index cf8c4724c5..1c3476c0a9 100644 --- a/lib/Target/ARM/ARMInstrFormats.td +++ b/lib/Target/ARM/ARMInstrFormats.td @@ -221,20 +221,25 @@ def neg_zero : Operand<i32> { let PrintMethod = "printNegZeroOperand"; } -// Narrow Shift Right Immediate - A narrow shift right immediate is encoded -// differently from other shift immediates. The imm6 field is encoded like so: +// Shift Right Immediate - A shift right immediate is encoded differently from +// other shift immediates. The imm6 field is encoded like so: // -// 16-bit: imm6<5:3> = '001', 8 - <imm> is encded in imm6<2:0> -// 32-bit: imm6<5:4> = '01',16 - <imm> is encded in imm6<3:0> -// 64-bit: imm6<5> = '1', 32 - <imm> is encded in imm6<4:0> -def nsr16_imm : Operand<i32> { - let EncoderMethod = "getNarrowShiftRight16Imm"; -} -def nsr32_imm : Operand<i32> { - let EncoderMethod = "getNarrowShiftRight32Imm"; -} -def nsr64_imm : Operand<i32> { - let EncoderMethod = "getNarrowShiftRight64Imm"; +// Offset Encoding +// 8 imm6<5:3> = '001', 8 - <imm> is encoded in imm6<2:0> +// 16 imm6<5:4> = '01', 16 - <imm> is encoded in imm6<3:0> +// 32 imm6<5> = '1', 32 - <imm> is encoded in imm6<4:0> +// 64 64 - <imm> is encoded in imm6<5:0> +def shr_imm8 : Operand<i32> { + let EncoderMethod = "getShiftRight8Imm"; +} +def shr_imm16 : Operand<i32> { + let EncoderMethod = "getShiftRight16Imm"; +} +def shr_imm32 : Operand<i32> { + let EncoderMethod = "getShiftRight32Imm"; +} +def shr_imm64 : Operand<i32> { + let EncoderMethod = "getShiftRight64Imm"; } //===----------------------------------------------------------------------===// diff --git a/lib/Target/ARM/ARMInstrNEON.td b/lib/Target/ARM/ARMInstrNEON.td index 5be6df5025..b979232d46 100644 --- a/lib/Target/ARM/ARMInstrNEON.td +++ b/lib/Target/ARM/ARMInstrNEON.td @@ -3154,17 +3154,17 @@ multiclass N2VNSh_HSD<bit op24, bit op23, bits<4> op11_8, bit op7, bit op6, SDNode OpNode> { def v8i8 : N2VNSh<op24, op23, op11_8, op7, op6, op4, itin, OpcodeStr, !strconcat(Dt, "16"), - v8i8, v8i16, nsr16_imm, OpNode> { + v8i8, v8i16, shr_imm8, OpNode> { let Inst{21-19} = 0b001; // imm6 = 001xxx } def v4i16 : N2VNSh<op24, op23, op11_8, op7, op6, op4, itin, OpcodeStr, !strconcat(Dt, "32"), - v4i16, v4i32, nsr32_imm, OpNode> { + v4i16, v4i32, shr_imm16, OpNode> { let Inst{21-20} = 0b01; // imm6 = 01xxxx } def v2i32 : N2VNSh<op24, op23, op11_8, op7, op6, op4, itin, OpcodeStr, !strconcat(Dt, "64"), - v2i32, v2i64, nsr64_imm, OpNode> { + v2i32, v2i64, shr_imm32, OpNode> { let Inst{21} = 0b1; // imm6 = 1xxxxx } } diff --git a/lib/Target/ARM/ARMMCCodeEmitter.cpp b/lib/Target/ARM/ARMMCCodeEmitter.cpp index 48884a1d71..10607b17c5 100644 --- a/lib/Target/ARM/ARMMCCodeEmitter.cpp +++ b/lib/Target/ARM/ARMMCCodeEmitter.cpp @@ -278,12 +278,14 @@ public: unsigned getAddrMode6OffsetOpValue(const MCInst &MI, unsigned Op, SmallVectorImpl<MCFixup> &Fixups) const; - unsigned getNarrowShiftRight16Imm(const MCInst &MI, unsigned Op, - SmallVectorImpl<MCFixup> &Fixups) const; - unsigned getNarrowShiftRight32Imm(const MCInst &MI, unsigned Op, - SmallVectorImpl<MCFixup> &Fixups) const; - unsigned getNarrowShiftRight64Imm(const MCInst &MI, unsigned Op, - SmallVectorImpl<MCFixup> &Fixups) const; + unsigned getShiftRight8Imm(const MCInst &MI, unsigned Op, + SmallVectorImpl<MCFixup> &Fixups) const; + unsigned getShiftRight16Imm(const MCInst &MI, unsigned Op, + SmallVectorImpl<MCFixup> &Fixups) const; + unsigned getShiftRight32Imm(const MCInst &MI, unsigned Op, + SmallVectorImpl<MCFixup> &Fixups) const; + unsigned getShiftRight64Imm(const MCInst &MI, unsigned Op, + SmallVectorImpl<MCFixup> &Fixups) const; unsigned NEONThumb2DataIPostEncoder(const MCInst &MI, unsigned EncodedValue) const; @@ -1209,23 +1211,29 @@ getAddrMode6OffsetOpValue(const MCInst &MI, unsigned Op, } unsigned ARMMCCodeEmitter:: -getNarrowShiftRight16Imm(const MCInst &MI, unsigned Op, - SmallVectorImpl<MCFixup> &Fixups) const { +getShiftRight8Imm(const MCInst &MI, unsigned Op, + SmallVectorImpl<MCFixup> &Fixups) const { return 8 - MI.getOperand(Op).getImm(); } unsigned ARMMCCodeEmitter:: -getNarrowShiftRight32Imm(const MCInst &MI, unsigned Op, - SmallVectorImpl<MCFixup> &Fixups) const { +getShiftRight16Imm(const MCInst &MI, unsigned Op, + SmallVectorImpl<MCFixup> &Fixups) const { return 16 - MI.getOperand(Op).getImm(); } unsigned ARMMCCodeEmitter:: -getNarrowShiftRight64Imm(const MCInst &MI, unsigned Op, - SmallVectorImpl<MCFixup> &Fixups) const { +getShiftRight32Imm(const MCInst &MI, unsigned Op, + SmallVectorImpl<MCFixup> &Fixups) const { return 32 - MI.getOperand(Op).getImm(); } +unsigned ARMMCCodeEmitter:: +getShiftRight64Imm(const MCInst &MI, unsigned Op, + SmallVectorImpl<MCFixup> &Fixups) const { + return 64 - MI.getOperand(Op).getImm(); +} + void ARMMCCodeEmitter:: EncodeInstruction(const MCInst &MI, raw_ostream &OS, SmallVectorImpl<MCFixup> &Fixups) const { |