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| author | James Molloy <james.molloy@arm.com> | 2014-01-20 17:14:48 +0000 |
|---|---|---|
| committer | James Molloy <james.molloy@arm.com> | 2014-01-20 17:14:48 +0000 |
| commit | 61a7bb039a1d218a17db16383ebed43abbdd1b2b (patch) | |
| tree | 7994a2b0a1bfcfd81306eea6cac55b059bd2ccec /lib/Target/ARM | |
| parent | 95dd2f4e8d93ed339eb6dc815b03bdc2f877992e (diff) | |
| download | llvm-61a7bb039a1d218a17db16383ebed43abbdd1b2b.tar.gz llvm-61a7bb039a1d218a17db16383ebed43abbdd1b2b.tar.bz2 llvm-61a7bb039a1d218a17db16383ebed43abbdd1b2b.tar.xz | |
Remove the useless pseudo instructions VDUPfdf and VDUPfqf, replacing them with patterns to match VDUPLN.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199675 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/ARM')
| -rw-r--r-- | lib/Target/ARM/ARMExpandPseudoInsts.cpp | 27 | ||||
| -rw-r--r-- | lib/Target/ARM/ARMInstrNEON.td | 10 |
2 files changed, 6 insertions, 31 deletions
diff --git a/lib/Target/ARM/ARMExpandPseudoInsts.cpp b/lib/Target/ARM/ARMExpandPseudoInsts.cpp index f2aba620d3..62f9e10252 100644 --- a/lib/Target/ARM/ARMExpandPseudoInsts.cpp +++ b/lib/Target/ARM/ARMExpandPseudoInsts.cpp @@ -1079,33 +1079,6 @@ bool ARMExpandPseudo::ExpandMI(MachineBasicBlock &MBB, MI.eraseFromParent(); return true; } - case ARM::VDUPfqf: - case ARM::VDUPfdf:{ - unsigned NewOpc = Opcode == ARM::VDUPfqf ? ARM::VDUPLN32q : - ARM::VDUPLN32d; - MachineInstrBuilder MIB = - BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(NewOpc)); - unsigned OpIdx = 0; - unsigned SrcReg = MI.getOperand(1).getReg(); - unsigned Lane = TRI->getEncodingValue(SrcReg) & 1; - unsigned DReg = TRI->getMatchingSuperReg(SrcReg, - Lane & 1 ? ARM::ssub_1 : ARM::ssub_0, - &ARM::DPR_VFP2RegClass); - // The lane is [0,1] for the containing DReg superregister. - // Copy the dst/src register operands. - MIB.addOperand(MI.getOperand(OpIdx++)); - MIB.addReg(DReg); - ++OpIdx; - // Add the lane select operand. - MIB.addImm(Lane); - // Add the predicate operands. - MIB.addOperand(MI.getOperand(OpIdx++)); - MIB.addOperand(MI.getOperand(OpIdx++)); - - TransferImpOps(MI, MIB, MIB); - MI.eraseFromParent(); - return true; - } case ARM::VLD2q8Pseudo: case ARM::VLD2q16Pseudo: diff --git a/lib/Target/ARM/ARMInstrNEON.td b/lib/Target/ARM/ARMInstrNEON.td index 0b05c08ed9..3d993eb964 100644 --- a/lib/Target/ARM/ARMInstrNEON.td +++ b/lib/Target/ARM/ARMInstrNEON.td @@ -5490,10 +5490,12 @@ def : Pat<(v4f32 (NEONvduplane (v4f32 QPR:$src), imm:$lane)), (DSubReg_i32_reg imm:$lane))), (SubReg_i32_lane imm:$lane)))>; -def VDUPfdf : PseudoNeonI<(outs DPR:$dst), (ins SPR:$src), IIC_VMOVD, "", - [(set DPR:$dst, (v2f32 (NEONvdup (f32 SPR:$src))))]>; -def VDUPfqf : PseudoNeonI<(outs QPR:$dst), (ins SPR:$src), IIC_VMOVD, "", - [(set QPR:$dst, (v4f32 (NEONvdup (f32 SPR:$src))))]>; +def : Pat<(v2f32 (NEONvdup (f32 SPR:$src))), + (v2f32 (VDUPLN32d (INSERT_SUBREG (v2f32 (IMPLICIT_DEF)), + SPR:$src, ssub_0), (i32 0)))>; +def : Pat<(v4f32 (NEONvdup (f32 SPR:$src))), + (v4f32 (VDUPLN32q (INSERT_SUBREG (v2f32 (IMPLICIT_DEF)), + SPR:$src, ssub_0), (i32 0)))>; // VMOVN : Vector Narrowing Move defm VMOVN : N2VN_HSD<0b11,0b11,0b10,0b00100,0,0, IIC_VMOVN, |