diff options
| author | Saleem Abdulrasool <compnerd@compnerd.org> | 2014-05-22 04:46:46 +0000 |
|---|---|---|
| committer | Saleem Abdulrasool <compnerd@compnerd.org> | 2014-05-22 04:46:46 +0000 |
| commit | 71ce2118bb80aab2bf4503477b0fdb90401bca98 (patch) | |
| tree | c6c33949cd41aae1a72bb6fdc7c1f5c1761e8197 /lib/Target/ARM | |
| parent | bce7d05ba9bf159da47af70f360c8ff7205c91a6 (diff) | |
| download | llvm-71ce2118bb80aab2bf4503477b0fdb90401bca98.tar.gz llvm-71ce2118bb80aab2bf4503477b0fdb90401bca98.tar.bz2 llvm-71ce2118bb80aab2bf4503477b0fdb90401bca98.tar.xz | |
ARM: introduce llvm.arm.undefined intrinsic
This intrinsic permits the emission of platform specific undefined sequences.
ARM has reserved the 0xde opcode which takes a single integer parameter (ignored
by the CPU). This permits the operating system to implement custom behaviour on
this trap. The llvm.arm.undefined intrinsic is meant to provide a means for
generating the target specific behaviour from the frontend. This is
particularly useful for Windows on ARM which has made use of a series of these
special opcodes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209390 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/ARM')
| -rw-r--r-- | lib/Target/ARM/ARMInstrInfo.td | 2 | ||||
| -rw-r--r-- | lib/Target/ARM/ARMInstrThumb.td | 4 | ||||
| -rw-r--r-- | lib/Target/ARM/ARMInstrThumb2.td | 4 |
3 files changed, 5 insertions, 5 deletions
diff --git a/lib/Target/ARM/ARMInstrInfo.td b/lib/Target/ARM/ARMInstrInfo.td index f642893161..718d5da9d0 100644 --- a/lib/Target/ARM/ARMInstrInfo.td +++ b/lib/Target/ARM/ARMInstrInfo.td @@ -1969,7 +1969,7 @@ def DBG : AI<(outs), (ins imm0_15:$opt), MiscFrm, NoItinerary, "dbg", "\t$opt", // A8.8.247 UDF - Undefined (Encoding A1) def UDF : AInoP<(outs), (ins imm0_65535:$imm16), MiscFrm, NoItinerary, - "udf", "\t$imm16", []> { + "udf", "\t$imm16", [(int_arm_undefined imm0_65535:$imm16)]> { bits<16> imm16; let Inst{31-28} = 0b1110; // AL let Inst{27-25} = 0b011; diff --git a/lib/Target/ARM/ARMInstrThumb.td b/lib/Target/ARM/ARMInstrThumb.td index ff3832d98b..e17f73af03 100644 --- a/lib/Target/ARM/ARMInstrThumb.td +++ b/lib/Target/ARM/ARMInstrThumb.td @@ -1194,8 +1194,8 @@ def tTST : // A8.6.230 Sched<[WriteALU]>; // A8.8.247 UDF - Undefined (Encoding T1) -def tUDF : TI<(outs), (ins imm0_255:$imm8), IIC_Br, "udf\t$imm8", []>, - Encoding16 { +def tUDF : TI<(outs), (ins imm0_255:$imm8), IIC_Br, "udf\t$imm8", + [(int_arm_undefined imm0_255:$imm8)]>, Encoding16 { bits<8> imm8; let Inst{15-12} = 0b1101; let Inst{11-8} = 0b1110; diff --git a/lib/Target/ARM/ARMInstrThumb2.td b/lib/Target/ARM/ARMInstrThumb2.td index 28f528a510..c30d6abbb2 100644 --- a/lib/Target/ARM/ARMInstrThumb2.td +++ b/lib/Target/ARM/ARMInstrThumb2.td @@ -2408,8 +2408,8 @@ def t2UBFX: T2TwoRegBitFI< } // A8.8.247 UDF - Undefined (Encoding T2) -def t2UDF - : T2XI<(outs), (ins imm0_65535:$imm16), IIC_Br, "udf.w\t$imm16", []> { +def t2UDF : T2XI<(outs), (ins imm0_65535:$imm16), IIC_Br, "udf.w\t$imm16", + [(int_arm_undefined imm0_65535:$imm16)]> { bits<16> imm16; let Inst{31-29} = 0b111; let Inst{28-27} = 0b10; |