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author | Arnold Schwaighofer <aschwaighofer@apple.com> | 2013-09-30 15:56:34 +0000 |
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committer | Arnold Schwaighofer <aschwaighofer@apple.com> | 2013-09-30 15:56:34 +0000 |
commit | 7373265e1a2042032dfa48f1d0accca4e5b68fe1 (patch) | |
tree | 6c632d57ae0a5610ae10b8629f5e1da93ca8b19b /lib/Target/ARM | |
parent | b313a93be77c88ddac3eee553bdf9199c26bfd74 (diff) | |
download | llvm-7373265e1a2042032dfa48f1d0accca4e5b68fe1.tar.gz llvm-7373265e1a2042032dfa48f1d0accca4e5b68fe1.tar.bz2 llvm-7373265e1a2042032dfa48f1d0accca4e5b68fe1.tar.xz |
Swift model: Fix uop description on some writes
Those writes really need two/three uops.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191677 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/ARM')
-rw-r--r-- | lib/Target/ARM/ARMScheduleSwift.td | 13 |
1 files changed, 11 insertions, 2 deletions
diff --git a/lib/Target/ARM/ARMScheduleSwift.td b/lib/Target/ARM/ARMScheduleSwift.td index 2a41616b40..8d7dbc2460 100644 --- a/lib/Target/ARM/ARMScheduleSwift.td +++ b/lib/Target/ARM/ARMScheduleSwift.td @@ -1345,20 +1345,25 @@ let SchedModel = SwiftModel in { // 4.2.20 Integer Load Signextended def SwiftWriteP2P01ThreeCycle : SchedWriteRes<[SwiftUnitP2, SwiftUnitP01]> { let Latency = 3; + let NumMicroOps = 2; } def SwiftWriteP2P01FourCyle : SchedWriteRes<[SwiftUnitP2, SwiftUnitP01]> { let Latency = 4; + let NumMicroOps = 2; } def SwiftWriteP2P01P01FourCycle : SchedWriteRes<[SwiftUnitP2, SwiftUnitP01, SwiftUnitP01]> { let Latency = 4; + let NumMicroOps = 3; } def SwiftWriteP2P2ThreeCycle : SchedWriteRes<[SwiftUnitP2, SwiftUnitP2]> { let Latency = 3; + let NumMicroOps = 2; } def SwiftWriteP2P2P01ThreeCycle : SchedWriteRes<[SwiftUnitP2, SwiftUnitP2, - SwiftUnitP01]> { + SwiftUnitP01]> { let Latency = 3; + let NumMicroOps = 3; } def SwiftWrBackOne : SchedWriteRes<[]> { let Latency = 1; @@ -1399,7 +1404,10 @@ let SchedModel = SwiftModel in { def SwiftWriteLM#Lat#Cy : SchedWriteRes<[SwiftUnitP2]> { let Latency = Lat; } - def SwiftWriteLM#Lat#CyNo : SchedWriteRes<[]> { let Latency = Lat; } + def SwiftWriteLM#Lat#CyNo : SchedWriteRes<[]> { + let Latency = Lat; + let NumMicroOps = 0; + } } // Predicate. foreach NumAddr = 1-16 in { @@ -1520,6 +1528,7 @@ let SchedModel = SwiftModel in { // 4.2.25 Integer Store, Multiple def SwiftWriteStIncAddr : SchedWriteRes<[SwiftUnitP2, SwiftUnitP01]> { let Latency = 0; + let NumMicroOps = 2; } foreach NumAddr = 1-16 in { def SwiftWriteSTM#NumAddr : WriteSequence<[SwiftWriteStIncAddr], NumAddr>; |