diff options
author | Christian Pirker <cpirker@a-bix.com> | 2014-05-14 16:59:44 +0000 |
---|---|---|
committer | Christian Pirker <cpirker@a-bix.com> | 2014-05-14 16:59:44 +0000 |
commit | 8101512a2d0cc68c0ad4637e0740f46b862c3df4 (patch) | |
tree | 4dc141d3926e1b8a73172211440c7e28991ec530 /lib/Target/ARM | |
parent | 62d6aa025207a032dbf0aef19f9b484926f01398 (diff) | |
download | llvm-8101512a2d0cc68c0ad4637e0740f46b862c3df4.tar.gz llvm-8101512a2d0cc68c0ad4637e0740f46b862c3df4.tar.bz2 llvm-8101512a2d0cc68c0ad4637e0740f46b862c3df4.tar.xz |
ARM-BE: test files for vector argument passing
Reviewed at http://reviews.llvm.org/D3766
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208793 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/ARM')
-rw-r--r-- | lib/Target/ARM/ARMISelLowering.cpp | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/lib/Target/ARM/ARMISelLowering.cpp b/lib/Target/ARM/ARMISelLowering.cpp index e8e28cac20..e7ffeee8f9 100644 --- a/lib/Target/ARM/ARMISelLowering.cpp +++ b/lib/Target/ARM/ARMISelLowering.cpp @@ -3965,7 +3965,8 @@ static SDValue ExpandBITCAST(SDNode *N, SelectionDAG &DAG) { // Turn f64->i64 into VMOVRRD. if (DstVT == MVT::i64 && TLI.isTypeLegal(SrcVT)) { SDValue Cvt; - if (TLI.isBigEndian() && SrcVT.isVector()) + if (TLI.isBigEndian() && SrcVT.isVector() && + SrcVT.getVectorNumElements() > 1) Cvt = DAG.getNode(ARMISD::VMOVRRD, dl, DAG.getVTList(MVT::i32, MVT::i32), DAG.getNode(ARMISD::VREV64, dl, SrcVT, Op)); |