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| author | Andrew Trick <atrick@apple.com> | 2013-12-28 21:57:00 +0000 |
|---|---|---|
| committer | Andrew Trick <atrick@apple.com> | 2013-12-28 21:57:00 +0000 |
| commit | 9eac3a79d9cca351ea2bef273c505acbc17eac07 (patch) | |
| tree | 94b30133a5a67e2749ccafb9e008abe9a76732e4 /lib/Target/ARM | |
| parent | 9e76e1d78504e6ef7782b87e87d99fb77de6bb86 (diff) | |
| download | llvm-9eac3a79d9cca351ea2bef273c505acbc17eac07.tar.gz llvm-9eac3a79d9cca351ea2bef273c505acbc17eac07.tar.bz2 llvm-9eac3a79d9cca351ea2bef273c505acbc17eac07.tar.xz | |
The Cortex-A9 machine model is incomplete. Mark it as such.
Many vector operations never had itineraries. Since the new machine
model was a mapping from existing itinerary classes, we don't have a
model for these. We still want to migrate A9 even though no one has
invested in a complete model, so mark it incomplete to avoid the
scheduler asserting.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198123 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/ARM')
| -rw-r--r-- | lib/Target/ARM/ARMScheduleA9.td | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/lib/Target/ARM/ARMScheduleA9.td b/lib/Target/ARM/ARMScheduleA9.td index 7d114a36b9..e4c2c753ae 100644 --- a/lib/Target/ARM/ARMScheduleA9.td +++ b/lib/Target/ARM/ARMScheduleA9.td @@ -1894,6 +1894,10 @@ def CortexA9Model : SchedMachineModel { let MispredictPenalty = 8; // Based on estimate of pipeline depth. let Itineraries = CortexA9Itineraries; + + // FIXME: Many vector operations were never given an itinerary. We + // haven't mapped these to the new model either. + let CompleteModel = 0; } //===----------------------------------------------------------------------===// @@ -2397,6 +2401,7 @@ def :ItinRW<[A9WriteV3, A9Read2], [IIC_VSUBiD, IIC_VSUBiQ, IIC_VCNTiD]>; // ... // VHADD/VRHADD/VQADD/VTST/VADH/VRADH def :ItinRW<[A9WriteV4, A9Read2, A9Read2], [IIC_VBINi4D, IIC_VBINi4Q]>; + // VSBH/VRSBH/VHSUB/VQSUB/VABD/VCEQ/VCGE/VCGT/VMAX/VMIN/VPMAX/VPMIN/VABDL def :ItinRW<[A9WriteV4, A9Read2], [IIC_VSUBi4D, IIC_VSUBi4Q]>; // VQNEG/VQABS |