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| author | Anton Korobeynikov <asl@math.spbu.ru> | 2010-04-07 18:19:46 +0000 |
|---|---|---|
| committer | Anton Korobeynikov <asl@math.spbu.ru> | 2010-04-07 18:19:46 +0000 |
| commit | c492e094553bcd64be999f5068eca8d04d872a8a (patch) | |
| tree | 4e9d190a92968834a1af2e89c8be6a616b7cf15f /lib/Target/ARM | |
| parent | 391b3431e2a9049fb1a5d51b6cca1c9a86d636c1 (diff) | |
| download | llvm-c492e094553bcd64be999f5068eca8d04d872a8a.tar.gz llvm-c492e094553bcd64be999f5068eca8d04d872a8a.tar.bz2 llvm-c492e094553bcd64be999f5068eca8d04d872a8a.tar.xz | |
Add new itin classes for FP16 <-> FP32 conversions and make uise of them for A9.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100647 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/ARM')
| -rw-r--r-- | lib/Target/ARM/ARMInstrVFP.td | 8 | ||||
| -rw-r--r-- | lib/Target/ARM/ARMSchedule.td | 2 | ||||
| -rw-r--r-- | lib/Target/ARM/ARMScheduleV7.td | 14 |
3 files changed, 20 insertions, 4 deletions
diff --git a/lib/Target/ARM/ARMInstrVFP.td b/lib/Target/ARM/ARMInstrVFP.td index 0458389286..0bc312a307 100644 --- a/lib/Target/ARM/ARMInstrVFP.td +++ b/lib/Target/ARM/ARMInstrVFP.td @@ -256,25 +256,25 @@ def VCVTSD : VFPAI<(outs SPR:$dst), (ins DPR:$a), VFPUnaryFrm, // Between half-precision and single-precision. For disassembly only. def VCVTBSH : ASuI<0b11101, 0b11, 0b0010, 0b01, 0, (outs SPR:$dst), (ins SPR:$a), - /* FIXME */ IIC_fpCVTDS, "vcvtb", ".f32.f16\t$dst, $a", + /* FIXME */ IIC_fpCVTSH, "vcvtb", ".f32.f16\t$dst, $a", [/* For disassembly only; pattern left blank */]>; def : ARMPat<(f32_to_f16 SPR:$a), (i32 (COPY_TO_REGCLASS (VCVTBSH SPR:$a), GPR))>; def VCVTBHS : ASuI<0b11101, 0b11, 0b0011, 0b01, 0, (outs SPR:$dst), (ins SPR:$a), - /* FIXME */ IIC_fpCVTDS, "vcvtb", ".f16.f32\t$dst, $a", + /* FIXME */ IIC_fpCVTHS, "vcvtb", ".f16.f32\t$dst, $a", [/* For disassembly only; pattern left blank */]>; def : ARMPat<(f16_to_f32 GPR:$a), (VCVTBHS (COPY_TO_REGCLASS GPR:$a, SPR))>; def VCVTTSH : ASuI<0b11101, 0b11, 0b0010, 0b11, 0, (outs SPR:$dst), (ins SPR:$a), - /* FIXME */ IIC_fpCVTDS, "vcvtt", ".f32.f16\t$dst, $a", + /* FIXME */ IIC_fpCVTSH, "vcvtt", ".f32.f16\t$dst, $a", [/* For disassembly only; pattern left blank */]>; def VCVTTHS : ASuI<0b11101, 0b11, 0b0011, 0b11, 0, (outs SPR:$dst), (ins SPR:$a), - /* FIXME */ IIC_fpCVTDS, "vcvtt", ".f16.f32\t$dst, $a", + /* FIXME */ IIC_fpCVTHS, "vcvtt", ".f16.f32\t$dst, $a", [/* For disassembly only; pattern left blank */]>; let neverHasSideEffects = 1 in { diff --git a/lib/Target/ARM/ARMSchedule.td b/lib/Target/ARM/ARMSchedule.td index db15a85e40..7a1c1e2b29 100644 --- a/lib/Target/ARM/ARMSchedule.td +++ b/lib/Target/ARM/ARMSchedule.td @@ -71,6 +71,8 @@ def IIC_fpCMP32 : InstrItinClass; def IIC_fpCMP64 : InstrItinClass; def IIC_fpCVTSD : InstrItinClass; def IIC_fpCVTDS : InstrItinClass; +def IIC_fpCVTSH : InstrItinClass; +def IIC_fpCVTHS : InstrItinClass; def IIC_fpCVTIS : InstrItinClass; def IIC_fpCVTID : InstrItinClass; def IIC_fpCVTSI : InstrItinClass; diff --git a/lib/Target/ARM/ARMScheduleV7.td b/lib/Target/ARM/ARMScheduleV7.td index 0d7a5539c1..a4931368c2 100644 --- a/lib/Target/ARM/ARMScheduleV7.td +++ b/lib/Target/ARM/ARMScheduleV7.td @@ -651,6 +651,20 @@ def CortexA9Itineraries : ProcessorItineraries<[ InstrStage2<5, [FU_DRegsN], 0, Reserved>, InstrStage<1, [FU_Pipe0, FU_Pipe1]>, InstrStage<1, [FU_NPipe]>], [4, 1]>, + + // + // Single to Half FP Convert + InstrItinData<IIC_fpCVTSH , [InstrStage2<1, [FU_DRegsVFP], 0, Required>, + InstrStage2<5, [FU_DRegsN], 0, Reserved>, + InstrStage<1, [FU_Pipe0, FU_Pipe1]>, + InstrStage<1, [FU_NPipe]>], [4, 1]>, + // + // Half to Single FP Convert + InstrItinData<IIC_fpCVTHS , [InstrStage2<1, [FU_DRegsVFP], 0, Required>, + InstrStage2<3, [FU_DRegsN], 0, Reserved>, + InstrStage<1, [FU_Pipe0, FU_Pipe1]>, + InstrStage<1, [FU_NPipe]>], [2, 1]>, + // // Single-Precision FP to Integer Convert InstrItinData<IIC_fpCVTSI , [InstrStage2<1, [FU_DRegsVFP], 0, Required>, |