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author | Tim Northover <tnorthover@apple.com> | 2014-05-27 10:43:38 +0000 |
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committer | Tim Northover <tnorthover@apple.com> | 2014-05-27 10:43:38 +0000 |
commit | e43c5023fe0c1de8d5c1ff13d07ff710b196d121 (patch) | |
tree | 9ed856584ebadab0711b006fd43537f23e3da0cd /lib/Target/ARM | |
parent | ae85c73d4af578822bb957d94d6385d73ff57b3b (diff) | |
download | llvm-e43c5023fe0c1de8d5c1ff13d07ff710b196d121.tar.gz llvm-e43c5023fe0c1de8d5c1ff13d07ff710b196d121.tar.bz2 llvm-e43c5023fe0c1de8d5c1ff13d07ff710b196d121.tar.xz |
ARM: teach AAPCS-VFP to deal with Cortex-M4.
Cortex-M4 only has single-precision floating point support, so any LLVM
"double" type will have been split into 2 i32s by now. Fortunately, the
consecutive-register framework turns out to be precisely what's needed to
reconstruct the double and follow AAPCS-VFP correctly!
rdar://problem/17012966
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209650 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/ARM')
-rw-r--r-- | lib/Target/ARM/ARMCallingConv.h | 17 | ||||
-rw-r--r-- | lib/Target/ARM/ARMISelLowering.cpp | 17 |
2 files changed, 21 insertions, 13 deletions
diff --git a/lib/Target/ARM/ARMCallingConv.h b/lib/Target/ARM/ARMCallingConv.h index 8e0fd89352..dc41c1c14b 100644 --- a/lib/Target/ARM/ARMCallingConv.h +++ b/lib/Target/ARM/ARMCallingConv.h @@ -177,9 +177,8 @@ static bool CC_ARM_AAPCS_Custom_HA(unsigned &ValNo, MVT &ValVT, MVT &LocVT, CCValAssign::LocInfo &LocInfo, ISD::ArgFlagsTy &ArgFlags, CCState &State) { SmallVectorImpl<CCValAssign> &PendingHAMembers = State.getPendingLocs(); - // AAPCS HFAs must have 1-4 elements, all of the same type - assert(PendingHAMembers.size() < 4); + assert(PendingHAMembers.size() < 8); if (PendingHAMembers.size() > 0) assert(PendingHAMembers[0].getLocVT() == LocVT); @@ -189,7 +188,7 @@ static bool CC_ARM_AAPCS_Custom_HA(unsigned &ValNo, MVT &ValVT, MVT &LocVT, CCValAssign::getPending(ValNo, ValVT, LocVT, LocInfo)); if (ArgFlags.isInConsecutiveRegsLast()) { - assert(PendingHAMembers.size() > 0 && PendingHAMembers.size() <= 4 && + assert(PendingHAMembers.size() > 0 && PendingHAMembers.size() <= 8 && "Homogeneous aggregates must have between 1 and 4 members"); // Try to allocate a contiguous block of registers, each of the correct @@ -197,6 +196,7 @@ static bool CC_ARM_AAPCS_Custom_HA(unsigned &ValNo, MVT &ValVT, MVT &LocVT, const uint16_t *RegList; unsigned NumRegs; switch (LocVT.SimpleTy) { + case MVT::i32: case MVT::f32: RegList = SRegList; NumRegs = 16; @@ -235,11 +235,20 @@ static bool CC_ARM_AAPCS_Custom_HA(unsigned &ValNo, MVT &ValVT, MVT &LocVT, State.AllocateReg(SRegList[regNo]); unsigned Size = LocVT.getSizeInBits() / 8; - unsigned Align = LocVT.SimpleTy == MVT::v2f64 ? 8 : Size; + unsigned Align = Size; + + if (LocVT.SimpleTy == MVT::v2f64 || LocVT.SimpleTy == MVT::i32) { + // Vectors are always aligned to 8 bytes. If we've seen an i32 here + // it's because it's been split from a larger type, also with align 8. + Align = 8; + } for (auto It : PendingHAMembers) { It.convertToMem(State.AllocateStack(Size, Align)); State.addLoc(It); + + // Only the first member needs to be aligned. + Align = 1; } // All pending members have now been allocated diff --git a/lib/Target/ARM/ARMISelLowering.cpp b/lib/Target/ARM/ARMISelLowering.cpp index 5beb752d3a..00d07e8406 100644 --- a/lib/Target/ARM/ARMISelLowering.cpp +++ b/lib/Target/ARM/ARMISelLowering.cpp @@ -10778,14 +10778,13 @@ static bool isHomogeneousAggregate(Type *Ty, HABaseType &Base, /// \brief Return true if a type is an AAPCS-VFP homogeneous aggregate. bool ARMTargetLowering::functionArgumentNeedsConsecutiveRegisters( Type *Ty, CallingConv::ID CallConv, bool isVarArg) const { - if (getEffectiveCallingConv(CallConv, isVarArg) == - CallingConv::ARM_AAPCS_VFP) { - HABaseType Base = HA_UNKNOWN; - uint64_t Members = 0; - bool result = isHomogeneousAggregate(Ty, Base, Members); - DEBUG(dbgs() << "isHA: " << result << " "; Ty->dump(); dbgs() << "\n"); - return result; - } else { + if (getEffectiveCallingConv(CallConv, isVarArg) != + CallingConv::ARM_AAPCS_VFP) return false; - } + + HABaseType Base = HA_UNKNOWN; + uint64_t Members = 0; + bool result = isHomogeneousAggregate(Ty, Base, Members); + DEBUG(dbgs() << "isHA: " << result << " "; Ty->dump(); dbgs() << "\n"); + return result; } |