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author | Bill Wendling <isanbard@gmail.com> | 2008-09-16 21:48:12 +0000 |
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committer | Bill Wendling <isanbard@gmail.com> | 2008-09-16 21:48:12 +0000 |
commit | 056292fd738924f3f7703725d8f630983794b5a5 (patch) | |
tree | f097aff34063d06c497f56489a186f411740cf34 /lib/Target/Alpha/AlphaISelLowering.cpp | |
parent | aed48bfee87046f40330fc35d17265dd3aaf5dd5 (diff) | |
download | llvm-056292fd738924f3f7703725d8f630983794b5a5.tar.gz llvm-056292fd738924f3f7703725d8f630983794b5a5.tar.bz2 llvm-056292fd738924f3f7703725d8f630983794b5a5.tar.xz |
Reverting r56249. On further investigation, this functionality isn't needed.
Apologies for the thrashing.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56251 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/Alpha/AlphaISelLowering.cpp')
-rw-r--r-- | lib/Target/Alpha/AlphaISelLowering.cpp | 17 |
1 files changed, 9 insertions, 8 deletions
diff --git a/lib/Target/Alpha/AlphaISelLowering.cpp b/lib/Target/Alpha/AlphaISelLowering.cpp index 26bc70a39b..5b7d1251a6 100644 --- a/lib/Target/Alpha/AlphaISelLowering.cpp +++ b/lib/Target/Alpha/AlphaISelLowering.cpp @@ -125,11 +125,12 @@ AlphaTargetLowering::AlphaTargetLowering(TargetMachine &TM) : TargetLowering(TM) setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand); setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64, Expand); - // We want to legalize GlobalAddress and ConstantPool and Symbols nodes into - // the appropriate instructions to materialize the address. + // We want to legalize GlobalAddress and ConstantPool and + // ExternalSymbols nodes into the appropriate instructions to + // materialize the address. setOperationAction(ISD::GlobalAddress, MVT::i64, Custom); setOperationAction(ISD::ConstantPool, MVT::i64, Custom); - setOperationAction(ISD::Symbol, MVT::i64, Custom); + setOperationAction(ISD::ExternalSymbol, MVT::i64, Custom); setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom); setOperationAction(ISD::VASTART, MVT::Other, Custom); @@ -490,13 +491,13 @@ SDValue AlphaTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) { return DAG.getNode(AlphaISD::RelLit, MVT::i64, GA, DAG.getNode(ISD::GLOBAL_OFFSET_TABLE, MVT::i64)); } - case ISD::Symbol: { - SymbolSDNode *S = cast<SymbolSDNode>(Op); + case ISD::ExternalSymbol: { return DAG.getNode(AlphaISD::RelLit, MVT::i64, - DAG.getTargetSymbol(S->getSymbol(), MVT::i64, - S->getLinkage()), + DAG.getTargetExternalSymbol(cast<ExternalSymbolSDNode>(Op) + ->getSymbol(), MVT::i64), DAG.getNode(ISD::GLOBAL_OFFSET_TABLE, MVT::i64)); } + case ISD::UREM: case ISD::SREM: //Expand only on constant case @@ -525,7 +526,7 @@ SDValue AlphaTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) { } SDValue Tmp1 = Op.getOperand(0), Tmp2 = Op.getOperand(1), - Addr = DAG.getSymbol(opstr, MVT::i64); + Addr = DAG.getExternalSymbol(opstr, MVT::i64); return DAG.getNode(AlphaISD::DivCall, MVT::i64, Addr, Tmp1, Tmp2); } break; |