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author | Reid Spencer <rspencer@reidspencer.com> | 2006-11-02 20:25:50 +0000 |
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committer | Reid Spencer <rspencer@reidspencer.com> | 2006-11-02 20:25:50 +0000 |
commit | 3ed469ccd7b028a030b550d84b7336d146f5d8fa (patch) | |
tree | 66c6b892b6330e9e2eacb4a2c4e4dacf078ee216 /lib/Target/Alpha/AlphaISelLowering.cpp | |
parent | ef42a01113a1ee8ef0f2c803ec05a5f20eca2854 (diff) | |
download | llvm-3ed469ccd7b028a030b550d84b7336d146f5d8fa.tar.gz llvm-3ed469ccd7b028a030b550d84b7336d146f5d8fa.tar.bz2 llvm-3ed469ccd7b028a030b550d84b7336d146f5d8fa.tar.xz |
For PR786:
Turn on -Wunused and -Wno-unused-parameter. Clean up most of the resulting
fall out by removing unused variables. Remaining warnings have to do with
unused functions (I didn't want to delete code without review) and unused
variables in generated code. Maintainers should clean up the remaining
issues when they see them. All changes pass DejaGnu tests and Olden.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31380 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/Alpha/AlphaISelLowering.cpp')
-rw-r--r-- | lib/Target/Alpha/AlphaISelLowering.cpp | 5 |
1 files changed, 0 insertions, 5 deletions
diff --git a/lib/Target/Alpha/AlphaISelLowering.cpp b/lib/Target/Alpha/AlphaISelLowering.cpp index 0b8961ed14..9728d88a38 100644 --- a/lib/Target/Alpha/AlphaISelLowering.cpp +++ b/lib/Target/Alpha/AlphaISelLowering.cpp @@ -175,8 +175,6 @@ static SDOperand LowerJumpTable(SDOperand Op, SelectionDAG &DAG) { SDOperand JTI = DAG.getTargetJumpTable(JT->getIndex(), PtrVT); SDOperand Zero = DAG.getConstant(0, PtrVT); - const TargetMachine &TM = DAG.getTarget(); - SDOperand Hi = DAG.getNode(AlphaISD::GPRelHi, MVT::i64, JTI, DAG.getNode(ISD::GLOBAL_OFFSET_TABLE, MVT::i64)); SDOperand Lo = DAG.getNode(AlphaISD::GPRelLo, MVT::i64, JTI, Hi); @@ -207,7 +205,6 @@ static SDOperand LowerFORMAL_ARGUMENTS(SDOperand Op, SelectionDAG &DAG, int &VarArgsOffset) { MachineFunction &MF = DAG.getMachineFunction(); MachineFrameInfo *MFI = MF.getFrameInfo(); - SSARegMap *RegMap = MF.getSSARegMap(); std::vector<SDOperand> ArgValues; SDOperand Root = Op.getOperand(0); @@ -225,7 +222,6 @@ static SDOperand LowerFORMAL_ARGUMENTS(SDOperand Op, SelectionDAG &DAG, SDOperand ArgVal; if (ArgNo < 6) { - unsigned Vreg; switch (ObjectVT) { default: std::cerr << "Unknown Type " << ObjectVT << "\n"; @@ -480,7 +476,6 @@ SDOperand AlphaTargetLowering::LowerOperation(SDOperand Op, SelectionDAG &DAG) { //Expand only on constant case if (Op.getOperand(1).getOpcode() == ISD::Constant) { MVT::ValueType VT = Op.Val->getValueType(0); - unsigned Opc = Op.Val->getOpcode() == ISD::UREM ? ISD::UDIV : ISD::SDIV; SDOperand Tmp1 = Op.Val->getOpcode() == ISD::UREM ? BuildUDIV(Op.Val, DAG, NULL) : BuildSDIV(Op.Val, DAG, NULL); |