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author | Andrew Lenharth <andrewl@lenharth.org> | 2006-01-23 21:51:33 +0000 |
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committer | Andrew Lenharth <andrewl@lenharth.org> | 2006-01-23 21:51:33 +0000 |
commit | 66e495820a9d992b26f60d1e118521efd7d9c922 (patch) | |
tree | c7c6669e4acc0b643f4d3daf6464a4a7c824e445 /lib/Target/Alpha/AlphaISelLowering.cpp | |
parent | 7cf11b4ab248d6ab7fb0d9df0b72baf158201abe (diff) | |
download | llvm-66e495820a9d992b26f60d1e118521efd7d9c922.tar.gz llvm-66e495820a9d992b26f60d1e118521efd7d9c922.tar.bz2 llvm-66e495820a9d992b26f60d1e118521efd7d9c922.tar.xz |
added stores to lsmark
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25552 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/Alpha/AlphaISelLowering.cpp')
-rw-r--r-- | lib/Target/Alpha/AlphaISelLowering.cpp | 51 |
1 files changed, 51 insertions, 0 deletions
diff --git a/lib/Target/Alpha/AlphaISelLowering.cpp b/lib/Target/Alpha/AlphaISelLowering.cpp index 79d09c0bab..3b9d32f6f6 100644 --- a/lib/Target/Alpha/AlphaISelLowering.cpp +++ b/lib/Target/Alpha/AlphaISelLowering.cpp @@ -166,6 +166,12 @@ const char *AlphaTargetLowering::getTargetNodeName(unsigned Opcode) const { case AlphaISD::LDL_: return "Alpha::LDL_"; case AlphaISD::LDWU_: return "Alpha::LDWU_"; case AlphaISD::LDBU_: return "Alpha::LDBU_"; + case AlphaISD::STQ_: return "Alpha::STQ_"; + case AlphaISD::STT_: return "Alpha::STT_"; + case AlphaISD::STS_: return "Alpha::STS_"; + case AlphaISD::STL_: return "Alpha::STL_"; + case AlphaISD::STW_: return "Alpha::STW_"; + case AlphaISD::STB_: return "Alpha::STB_"; } } @@ -631,6 +637,51 @@ SDOperand AlphaTargetLowering::LowerOperation(SDOperand Op, SelectionDAG &DAG) { return DAG.getNode(Opc, VTS, ARGS); } + case ISD::TRUNCSTORE: + case ISD::STORE: + { + SDOperand Chain = Op.getOperand(0); + SDOperand Value = Op.getOperand(1); + SDOperand Address = Op.getOperand(2); + + unsigned Opc; + unsigned opcode = Op.getOpcode(); + + if (opcode == ISD::STORE) { + switch(Value.getValueType()) { + default: assert(0 && "unknown Type in store"); + case MVT::i64: Opc = AlphaISD::STQ_; break; + case MVT::f64: Opc = AlphaISD::STT_; break; + case MVT::f32: Opc = AlphaISD::STS_; break; + } + } else { //ISD::TRUNCSTORE + switch(cast<VTSDNode>(Op.getOperand(4))->getVT()) { + default: assert(0 && "unknown Type in store"); + case MVT::i8: Opc = AlphaISD::STB_; break; + case MVT::i16: Opc = AlphaISD::STW_; break; + case MVT::i32: Opc = AlphaISD::STL_; break; + } + } + + int i, j, k; + getValueInfo(cast<SrcValueSDNode>(Op.getOperand(3))->getValue(), i, j, k); + + SDOperand Zero = DAG.getConstant(0, MVT::i64); + std::vector<MVT::ValueType> VTS; + VTS.push_back(MVT::Other); + std::vector<SDOperand> ARGS; + ARGS.push_back(Chain); + ARGS.push_back(Value); + ARGS.push_back(Zero); + ARGS.push_back(Address); + ARGS.push_back(DAG.getConstant(i, MVT::i64)); + ARGS.push_back(DAG.getConstant(j, MVT::i64)); + ARGS.push_back(DAG.getConstant(k, MVT::i64)); + ARGS.push_back(DAG.getConstant(getUID(), MVT::i64)); + return DAG.getNode(Opc, VTS, ARGS); + } + + } return SDOperand(); |