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| author | Eli Friedman <eli.friedman@gmail.com> | 2009-07-24 07:43:59 +0000 |
|---|---|---|
| committer | Eli Friedman <eli.friedman@gmail.com> | 2009-07-24 07:43:59 +0000 |
| commit | 23ed52752bb40a9085c9d36bbc6603972c3e0080 (patch) | |
| tree | 20e0ea1df0d0ad6dcb38ed0cf471061324cc5052 /lib/Target/Alpha/AlphaInstrInfo.cpp | |
| parent | 050578fb4a006d7a183662f83fc22f7c78475605 (diff) | |
| download | llvm-23ed52752bb40a9085c9d36bbc6603972c3e0080.tar.gz llvm-23ed52752bb40a9085c9d36bbc6603972c3e0080.tar.bz2 llvm-23ed52752bb40a9085c9d36bbc6603972c3e0080.tar.xz | |
Remove unused member functions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76960 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/Alpha/AlphaInstrInfo.cpp')
| -rw-r--r-- | lib/Target/Alpha/AlphaInstrInfo.cpp | 43 |
1 files changed, 0 insertions, 43 deletions
diff --git a/lib/Target/Alpha/AlphaInstrInfo.cpp b/lib/Target/Alpha/AlphaInstrInfo.cpp index 3cb2ce3720..86173ff272 100644 --- a/lib/Target/Alpha/AlphaInstrInfo.cpp +++ b/lib/Target/Alpha/AlphaInstrInfo.cpp @@ -204,28 +204,6 @@ AlphaInstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB, llvm_unreachable("Unhandled register class"); } -void AlphaInstrInfo::storeRegToAddr(MachineFunction &MF, unsigned SrcReg, - bool isKill, - SmallVectorImpl<MachineOperand> &Addr, - const TargetRegisterClass *RC, - SmallVectorImpl<MachineInstr*> &NewMIs) const { - unsigned Opc = 0; - if (RC == Alpha::F4RCRegisterClass) - Opc = Alpha::STS; - else if (RC == Alpha::F8RCRegisterClass) - Opc = Alpha::STT; - else if (RC == Alpha::GPRCRegisterClass) - Opc = Alpha::STQ; - else - llvm_unreachable("Unhandled register class"); - DebugLoc DL = DebugLoc::getUnknownLoc(); - MachineInstrBuilder MIB = - BuildMI(MF, DL, get(Opc)).addReg(SrcReg, getKillRegState(isKill)); - for (unsigned i = 0, e = Addr.size(); i != e; ++i) - MIB.addOperand(Addr[i]); - NewMIs.push_back(MIB); -} - void AlphaInstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, @@ -249,27 +227,6 @@ AlphaInstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB, llvm_unreachable("Unhandled register class"); } -void AlphaInstrInfo::loadRegFromAddr(MachineFunction &MF, unsigned DestReg, - SmallVectorImpl<MachineOperand> &Addr, - const TargetRegisterClass *RC, - SmallVectorImpl<MachineInstr*> &NewMIs) const { - unsigned Opc = 0; - if (RC == Alpha::F4RCRegisterClass) - Opc = Alpha::LDS; - else if (RC == Alpha::F8RCRegisterClass) - Opc = Alpha::LDT; - else if (RC == Alpha::GPRCRegisterClass) - Opc = Alpha::LDQ; - else - llvm_unreachable("Unhandled register class"); - DebugLoc DL = DebugLoc::getUnknownLoc(); - MachineInstrBuilder MIB = - BuildMI(MF, DL, get(Opc), DestReg); - for (unsigned i = 0, e = Addr.size(); i != e; ++i) - MIB.addOperand(Addr[i]); - NewMIs.push_back(MIB); -} - MachineInstr *AlphaInstrInfo::foldMemoryOperandImpl(MachineFunction &MF, MachineInstr *MI, const SmallVectorImpl<unsigned> &Ops, |