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| author | Evan Cheng <evan.cheng@apple.com> | 2006-11-27 23:37:22 +0000 |
|---|---|---|
| committer | Evan Cheng <evan.cheng@apple.com> | 2006-11-27 23:37:22 +0000 |
| commit | c0f64ffab93d11fb27a3b8a0707b77400918a20e (patch) | |
| tree | cc2cfef30bfb1344f83d8cfd08aace72274bde47 /lib/Target/Alpha/AlphaInstrInfo.cpp | |
| parent | 722a0cafbd47eb6b8bf9a9e9dce2f6cb8383fef1 (diff) | |
| download | llvm-c0f64ffab93d11fb27a3b8a0707b77400918a20e.tar.gz llvm-c0f64ffab93d11fb27a3b8a0707b77400918a20e.tar.bz2 llvm-c0f64ffab93d11fb27a3b8a0707b77400918a20e.tar.xz | |
Change MachineInstr ctor's to take a TargetInstrDescriptor reference instead
of opcode and number of operands.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31947 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/Alpha/AlphaInstrInfo.cpp')
| -rw-r--r-- | lib/Target/Alpha/AlphaInstrInfo.cpp | 14 |
1 files changed, 7 insertions, 7 deletions
diff --git a/lib/Target/Alpha/AlphaInstrInfo.cpp b/lib/Target/Alpha/AlphaInstrInfo.cpp index 96514d9332..4ac352b674 100644 --- a/lib/Target/Alpha/AlphaInstrInfo.cpp +++ b/lib/Target/Alpha/AlphaInstrInfo.cpp @@ -110,25 +110,25 @@ void AlphaInstrInfo::InsertBranch(MachineBasicBlock &MBB,MachineBasicBlock *TBB, // One-way branch. if (FBB == 0) { if (Cond.empty()) // Unconditional branch - BuildMI(&MBB, Alpha::BR, 1).addMBB(TBB); + BuildMI(&MBB, get(Alpha::BR)).addMBB(TBB); else // Conditional branch if (isAlphaIntCondCode(Cond[0].getImm())) - BuildMI(&MBB, Alpha::COND_BRANCH_I, 3) + BuildMI(&MBB, get(Alpha::COND_BRANCH_I)) .addImm(Cond[0].getImm()).addReg(Cond[1].getReg()).addMBB(TBB); else - BuildMI(&MBB, Alpha::COND_BRANCH_F, 3) + BuildMI(&MBB, get(Alpha::COND_BRANCH_F)) .addImm(Cond[0].getImm()).addReg(Cond[1].getReg()).addMBB(TBB); return; } // Two-way Conditional Branch. if (isAlphaIntCondCode(Cond[0].getImm())) - BuildMI(&MBB, Alpha::COND_BRANCH_I, 3) + BuildMI(&MBB, get(Alpha::COND_BRANCH_I)) .addImm(Cond[0].getImm()).addReg(Cond[1].getReg()).addMBB(TBB); else - BuildMI(&MBB, Alpha::COND_BRANCH_F, 3) + BuildMI(&MBB, get(Alpha::COND_BRANCH_F)) .addImm(Cond[0].getImm()).addReg(Cond[1].getReg()).addMBB(TBB); - BuildMI(&MBB, Alpha::BR, 1).addMBB(FBB); + BuildMI(&MBB, get(Alpha::BR)).addMBB(FBB); } static unsigned AlphaRevCondCode(unsigned Opcode) { @@ -230,7 +230,7 @@ void AlphaInstrInfo::RemoveBranch(MachineBasicBlock &MBB) const { void AlphaInstrInfo::insertNoop(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI) const { - BuildMI(MBB, MI, Alpha::BISr, 2, Alpha::R31).addReg(Alpha::R31) + BuildMI(MBB, MI, get(Alpha::BISr), Alpha::R31).addReg(Alpha::R31) .addReg(Alpha::R31); } |