diff options
author | Owen Anderson <resistor@mac.com> | 2007-12-31 06:32:00 +0000 |
---|---|---|
committer | Owen Anderson <resistor@mac.com> | 2007-12-31 06:32:00 +0000 |
commit | d10fd9791c20fd8368fa0ce94b626b769c6c8ba0 (patch) | |
tree | 15d4f8237ffa7600737fab617923b5bef3267b16 /lib/Target/Alpha/AlphaInstrInfo.cpp | |
parent | f20c1a497fe3922ac718429d65a5fe396890575e (diff) | |
download | llvm-d10fd9791c20fd8368fa0ce94b626b769c6c8ba0.tar.gz llvm-d10fd9791c20fd8368fa0ce94b626b769c6c8ba0.tar.bz2 llvm-d10fd9791c20fd8368fa0ce94b626b769c6c8ba0.tar.xz |
Move copyRegToReg from MRegisterInfo to TargetInstrInfo. This is part of the
Machine-level API cleanup instigated by Chris.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45470 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/Alpha/AlphaInstrInfo.cpp')
-rw-r--r-- | lib/Target/Alpha/AlphaInstrInfo.cpp | 23 |
1 files changed, 23 insertions, 0 deletions
diff --git a/lib/Target/Alpha/AlphaInstrInfo.cpp b/lib/Target/Alpha/AlphaInstrInfo.cpp index aa7d10a36c..db0dc7b251 100644 --- a/lib/Target/Alpha/AlphaInstrInfo.cpp +++ b/lib/Target/Alpha/AlphaInstrInfo.cpp @@ -132,6 +132,29 @@ unsigned AlphaInstrInfo::InsertBranch(MachineBasicBlock &MBB,MachineBasicBlock * return 2; } +void AlphaInstrInfo::copyRegToReg(MachineBasicBlock &MBB, + MachineBasicBlock::iterator MI, + unsigned DestReg, unsigned SrcReg, + const TargetRegisterClass *DestRC, + const TargetRegisterClass *SrcRC) const { + //cerr << "copyRegToReg " << DestReg << " <- " << SrcReg << "\n"; + if (DestRC != SrcRC) { + cerr << "Not yet supported!"; + abort(); + } + + if (DestRC == Alpha::GPRCRegisterClass) { + BuildMI(MBB, MI, get(Alpha::BISr), DestReg).addReg(SrcReg).addReg(SrcReg); + } else if (DestRC == Alpha::F4RCRegisterClass) { + BuildMI(MBB, MI, get(Alpha::CPYSS), DestReg).addReg(SrcReg).addReg(SrcReg); + } else if (DestRC == Alpha::F8RCRegisterClass) { + BuildMI(MBB, MI, get(Alpha::CPYST), DestReg).addReg(SrcReg).addReg(SrcReg); + } else { + cerr << "Attempt to copy register that is not GPR or FPR"; + abort(); + } +} + static unsigned AlphaRevCondCode(unsigned Opcode) { switch (Opcode) { case Alpha::BEQ: return Alpha::BNE; |