Alpha Scheduling classes

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26643 91177308-0d34-0410-b5e6-96231b3b80d8

6 files changed, 333 insertions, 232 deletions

diff --git a/lib/Target/Alpha/Alpha.td b/lib/Target/Alpha/Alpha.td
index 3c78361846..80f03fbe86 100644
--- a/lib/Target/Alpha/Alpha.td
+++ b/lib/Target/Alpha/Alpha.td
@@ -32,6 +32,12 @@ def FeatureFIX : SubtargetFeature<"FIX", "HasF2I", "true",
 include "AlphaRegisterInfo.td"
 
 //===----------------------------------------------------------------------===//
+// Schedule Description
+//===----------------------------------------------------------------------===//
+
+include "AlphaSchedule.td"
+
+//===----------------------------------------------------------------------===//
 // Instruction Descriptions
 //===----------------------------------------------------------------------===//
 
@@ -47,11 +53,11 @@ def AlphaInstrInfo : InstrInfo {
 // Alpha Processor Definitions
 //===----------------------------------------------------------------------===//
 
-def : Processor<"generic", NoItineraries, []>;
-def : Processor<"pca56"  , NoItineraries, []>;
-def : Processor<"ev56"   , NoItineraries, []>;
-def : Processor<"ev6"    , NoItineraries, [FeatureFIX]>;
-def : Processor<"ev67"   , NoItineraries, [FeatureFIX, FeatureCIX]>;
+def : Processor<"generic", Alpha21264Itineraries, []>;
+def : Processor<"pca56"  , Alpha21264Itineraries, []>;
+def : Processor<"ev56"   , Alpha21264Itineraries, []>;
+def : Processor<"ev6"    , Alpha21264Itineraries, [FeatureFIX]>;
+def : Processor<"ev67"   , Alpha21264Itineraries, [FeatureFIX, FeatureCIX]>;
 
 //===----------------------------------------------------------------------===//
 // The Alpha Target
diff --git a/lib/Target/Alpha/AlphaISelLowering.h b/lib/Target/Alpha/AlphaISelLowering.h
index fcbaaac190..569fa74a8c 100644
--- a/lib/Target/Alpha/AlphaISelLowering.h
+++ b/lib/Target/Alpha/AlphaISelLowering.h
@@ -44,9 +44,6 @@ namespace llvm {
       /// DIVCALL - used for special library calls for div and rem
       DivCall,
 
-      ///LD, ST
-      LDQ_, LDT_, LDS_, LDL_, LDWU_, LDBU_, 
-      STQ_, STT_, STS_, STL_, STW_, STB_, 
     };
   }
 
diff --git a/lib/Target/Alpha/AlphaInstrFormats.td b/lib/Target/Alpha/AlphaInstrFormats.td
index c29a7cebce..663562948d 100644
--- a/lib/Target/Alpha/AlphaInstrFormats.td
+++ b/lib/Target/Alpha/AlphaInstrFormats.td
@@ -27,21 +27,18 @@ def s64imm  : Operand<i64>;
 // Instruction format superclass
 //===----------------------------------------------------------------------===//
 // Alpha instruction baseline
-class InstAlphaAlt<bits<6> op, string asmstr> : Instruction {
+class InstAlpha<bits<6> op, string asmstr, InstrItinClass itin> : Instruction {
   field bits<32> Inst;
   let Namespace = "Alpha";
   let AsmString = asmstr;
   let Inst{31-26} = op;
+  let Itinerary = itin;
 }
 
-class InstAlpha<bits<6> op, dag OL, string asmstr> 
-: InstAlphaAlt<op, asmstr> { // Alpha instruction baseline
-  let OperandList = OL;
-}
 
 //3.3.1
-class MForm<bits<6> opcode, bit store, bit load, string asmstr, list<dag> pattern> 
-        : InstAlphaAlt<opcode, asmstr> {
+class MForm<bits<6> opcode, bit store, bit load, string asmstr, list<dag> pattern, InstrItinClass itin> 
+        : InstAlpha<opcode, asmstr, itin> {
   let Pattern = pattern;
   let isStore = store;
   let isLoad = load;
@@ -55,21 +52,24 @@ class MForm<bits<6> opcode, bit store, bit load, string asmstr, list<dag> patter
   let Inst{20-16} = Rb;
   let Inst{15-0} = disp;
 }
-
-class MfcForm<bits<6> opcode, bits<16> fc, string asmstr> 
-        : InstAlpha<opcode, (ops GPRC:$RA), asmstr> {
+class MfcForm<bits<6> opcode, bits<16> fc, string asmstr, InstrItinClass itin> 
+        : InstAlpha<opcode, asmstr, itin> {    
   bits<5> Ra;
 
+  let OperandList = (ops GPRC:$RA);
   let Inst{25-21} = Ra;
   let Inst{20-16} = 0;
   let Inst{15-0} = fc;
 }
 
-class MbrForm<bits<6> opcode, bits<2> TB, dag OL, string asmstr> : InstAlpha<opcode, OL, asmstr> {
+class MbrForm<bits<6> opcode, bits<2> TB, dag OL, string asmstr, InstrItinClass itin>
+    : InstAlpha<opcode, asmstr, itin> {
   bits<5> Ra;
   bits<5> Rb;
   bits<14> disp;
 
+  let OperandList = OL;
+
   let Inst{25-21} = Ra;
   let Inst{20-16} = Rb;
   let Inst{15-14} = TB;
@@ -79,10 +79,10 @@ class MbrForm<bits<6> opcode, bits<2> TB, dag OL, string asmstr> : InstAlpha<opc
 //3.3.2
 def target : Operand<OtherVT> {}
 let isBranch = 1, isTerminator = 1 in
-class BFormD<bits<6> opcode, string asmstr, list<dag> pattern> 
-    : InstAlpha<opcode, (ops target:$DISP), asmstr> {
+class BFormD<bits<6> opcode, string asmstr, list<dag> pattern, InstrItinClass itin> 
+    : InstAlpha<opcode, asmstr, itin> {
   let Pattern = pattern;
-
+  let OperandList = (ops target:$DISP);
   bits<5> Ra;
   bits<21> disp;
 
@@ -90,9 +90,10 @@ class BFormD<bits<6> opcode, string asmstr, list<dag> pattern>
   let Inst{20-0} = disp;
 }
 let isBranch = 1, isTerminator = 1 in
-class BForm<bits<6> opcode, string asmstr, list<dag> pattern> 
-    : InstAlpha<opcode, (ops GPRC:$RA, target:$DISP), asmstr> {
+class BForm<bits<6> opcode, string asmstr, list<dag> pattern, InstrItinClass itin> 
+    : InstAlpha<opcode, asmstr, itin> {
   let Pattern = pattern;
+  let OperandList = (ops GPRC:$RA, target:$DISP);
 
   bits<5> Ra;
   bits<21> disp;
@@ -102,9 +103,10 @@ class BForm<bits<6> opcode, string asmstr, list<dag> pattern>
 }
 
 let isBranch = 1, isTerminator = 1 in
-class FBForm<bits<6> opcode, string asmstr, list<dag> pattern> 
-    : InstAlpha<opcode, (ops F8RC:$RA, target:$DISP), asmstr> {
+class FBForm<bits<6> opcode, string asmstr, list<dag> pattern, InstrItinClass itin> 
+    : InstAlpha<opcode, asmstr, itin> {
   let Pattern = pattern;
+  let OperandList = (ops F8RC:$RA, target:$DISP);
 
   bits<5> Ra;
   bits<21> disp;
@@ -114,9 +116,10 @@ class FBForm<bits<6> opcode, string asmstr, list<dag> pattern>
 }
 
 //3.3.3
-class OForm<bits<6> opcode, bits<7> fun, string asmstr, list<dag> pattern> 
-        : InstAlpha<opcode, (ops GPRC:$RC, GPRC:$RA, GPRC:$RB), asmstr> {
+class OForm<bits<6> opcode, bits<7> fun, string asmstr, list<dag> pattern, InstrItinClass itin> 
+    : InstAlpha<opcode, asmstr, itin> {
   let Pattern = pattern;
+  let OperandList = (ops GPRC:$RC, GPRC:$RA, GPRC:$RB);
 
   bits<5> Rc;
   bits<5> Ra;
@@ -131,9 +134,10 @@ class OForm<bits<6> opcode, bits<7> fun, string asmstr, list<dag> pattern>
   let Inst{4-0} = Rc;
 }
 
-class OForm2<bits<6> opcode, bits<7> fun, string asmstr, list<dag> pattern> 
-        : InstAlpha<opcode, (ops GPRC:$RC, GPRC:$RB), asmstr> {
+class OForm2<bits<6> opcode, bits<7> fun, string asmstr, list<dag> pattern, InstrItinClass itin> 
+    : InstAlpha<opcode, asmstr, itin> {
   let Pattern = pattern;
+  let OperandList = (ops GPRC:$RC, GPRC:$RB);
 
   bits<5> Rc;
   bits<5> Rb;
@@ -147,9 +151,10 @@ class OForm2<bits<6> opcode, bits<7> fun, string asmstr, list<dag> pattern>
   let Inst{4-0} = Rc;
 }
 
-class OForm4<bits<6> opcode, bits<7> fun, string asmstr, list<dag> pattern> 
-        : InstAlpha<opcode, (ops GPRC:$RDEST, GPRC:$RFALSE, GPRC:$RTRUE, GPRC:$RCOND), asmstr> {
+class OForm4<bits<6> opcode, bits<7> fun, string asmstr, list<dag> pattern, InstrItinClass itin> 
+    : InstAlpha<opcode, asmstr, itin> {
   let Pattern = pattern;
+  let OperandList = (ops GPRC:$RDEST, GPRC:$RFALSE, GPRC:$RTRUE, GPRC:$RCOND);
 
   bits<5> Rc;
   bits<5> Rb;
@@ -166,9 +171,10 @@ class OForm4<bits<6> opcode, bits<7> fun, string asmstr, list<dag> pattern>
 }
 
 
-class OFormL<bits<6> opcode, bits<7> fun, string asmstr, list<dag> pattern> 
-        : InstAlpha<opcode, (ops GPRC:$RC, GPRC:$RA, u8imm:$L), asmstr> {
+class OFormL<bits<6> opcode, bits<7> fun, string asmstr, list<dag> pattern, InstrItinClass itin> 
+    : InstAlpha<opcode, asmstr, itin> {
   let Pattern = pattern;
+  let OperandList = (ops GPRC:$RC, GPRC:$RA, u8imm:$L);
 
   bits<5> Rc;
   bits<5> Ra;
@@ -182,10 +188,11 @@ class OFormL<bits<6> opcode, bits<7> fun, string asmstr, list<dag> pattern>
   let Inst{4-0} = Rc;
 }
 
-class OForm4L<bits<6> opcode, bits<7> fun, string asmstr, list<dag> pattern> 
-        : InstAlpha<opcode, (ops GPRC:$RDEST, GPRC:$RFALSE, s64imm:$RTRUE, GPRC:$RCOND), asmstr> {
+class OForm4L<bits<6> opcode, bits<7> fun, string asmstr, list<dag> pattern, InstrItinClass itin> 
+    : InstAlpha<opcode, asmstr, itin> {
   let Pattern = pattern;
-
+  let OperandList = (ops GPRC:$RDEST, GPRC:$RFALSE, s64imm:$RTRUE, GPRC:$RCOND);
+ 
   bits<5> Rc;
   bits<8> LIT;
   bits<5> Ra;
@@ -200,8 +207,8 @@ class OForm4L<bits<6> opcode, bits<7> fun, string asmstr, list<dag> pattern>
 }
 
 //3.3.4
-class FPForm<bits<6> opcode, bits<11> fun, string asmstr, list<dag> pattern> 
-        : InstAlphaAlt<opcode, asmstr> {
+class FPForm<bits<6> opcode, bits<11> fun, string asmstr, list<dag> pattern, InstrItinClass itin> 
+    : InstAlpha<opcode, asmstr, itin> {
   let Pattern = pattern;
 
   bits<5> Fc;
@@ -216,7 +223,9 @@ class FPForm<bits<6> opcode, bits<11> fun, string asmstr, list<dag> pattern>
 }
 
 //3.3.5
-class PALForm<bits<6> opcode, dag OL, string asmstr> : InstAlpha<opcode, OL, asmstr> {
+class PALForm<bits<6> opcode, dag OL, string asmstr, InstrItinClass itin>
+    : InstAlpha<opcode, asmstr, itin> {
+  let OperandList = OL;
   bits<26> Function;
 
   let Inst{25-0} = Function;
@@ -224,7 +233,9 @@ class PALForm<bits<6> opcode, dag OL, string asmstr> : InstAlpha<opcode, OL, asm
 
 
 // Pseudo instructions.
-class PseudoInstAlpha<dag OL, string nm, list<dag> pattern> : InstAlpha<0, OL, nm>  {
+class PseudoInstAlpha<dag OL, string nm, list<dag> pattern, InstrItinClass itin> 
+    : InstAlpha<0, nm, itin>  {
+  let OperandList = OL;
   let Pattern = pattern;
 
 }
diff --git a/lib/Target/Alpha/AlphaInstrInfo.td b/lib/Target/Alpha/AlphaInstrInfo.td
index dce3c0beb7..6d5458d255 100644
--- a/lib/Target/Alpha/AlphaInstrInfo.td
+++ b/lib/Target/Alpha/AlphaInstrInfo.td
@@ -95,24 +95,24 @@ def sub8  : PatFrag<(ops node:$op1, node:$op2),
 //Pseudo ops for selection
 
 def IDEF_I : PseudoInstAlpha<(ops GPRC:$RA), "#idef $RA",
-             [(set GPRC:$RA, (undef))]>;
+             [(set GPRC:$RA, (undef))], s_pseudo>;
 def IDEF_F32 : PseudoInstAlpha<(ops F4RC:$RA), "#idef $RA",
-             [(set F4RC:$RA, (undef))]>;
+             [(set F4RC:$RA, (undef))], s_pseudo>;
 def IDEF_F64 : PseudoInstAlpha<(ops F8RC:$RA), "#idef $RA",
-             [(set F8RC:$RA, (undef))]>;
+             [(set F8RC:$RA, (undef))], s_pseudo>;
 
-def WTF : PseudoInstAlpha<(ops variable_ops), "#wtf", []>;
+def WTF : PseudoInstAlpha<(ops variable_ops), "#wtf", [], s_pseudo>;
 
 let isLoad = 1, hasCtrlDep = 1 in {
 def ADJUSTSTACKUP : PseudoInstAlpha<(ops s64imm:$amt), "; ADJUP $amt", 
-                [(callseq_start imm:$amt)]>;
+                [(callseq_start imm:$amt)], s_pseudo>;
 def ADJUSTSTACKDOWN : PseudoInstAlpha<(ops s64imm:$amt), "; ADJDOWN $amt", 
-                [(callseq_end imm:$amt)]>;
+                [(callseq_end imm:$amt)], s_pseudo>;
 }
-def ALTENT : PseudoInstAlpha<(ops s64imm:$TARGET), "$$$TARGET..ng:\n", []>;
-def PCLABEL : PseudoInstAlpha<(ops s64imm:$num), "PCMARKER_$num:\n",[]>;
+def ALTENT : PseudoInstAlpha<(ops s64imm:$TARGET), "$$$TARGET..ng:\n", [], s_pseudo>;
+def PCLABEL : PseudoInstAlpha<(ops s64imm:$num), "PCMARKER_$num:\n",[], s_pseudo>;
 def MEMLABEL : PseudoInstAlpha<(ops s64imm:$i, s64imm:$j, s64imm:$k, s64imm:$m),
-         "LSMARKER$$$i$$$j$$$k$$$m:", []>;
+         "LSMARKER$$$i$$$j$$$k$$$m:", [], s_pseudo>;
 
 
 //***********************
@@ -124,38 +124,38 @@ def MEMLABEL : PseudoInstAlpha<(ops s64imm:$i, s64imm:$j, s64imm:$k, s64imm:$m),
 //conditional moves, int
 
 def CMOVLBC  : OForm4<  0x11, 0x16, "cmovlbc $RCOND,$RTRUE,$RDEST",
-                [(set GPRC:$RDEST, (select (xor GPRC:$RCOND, 1), GPRC:$RTRUE, GPRC:$RFALSE))]>;
+                [(set GPRC:$RDEST, (select (xor GPRC:$RCOND, 1), GPRC:$RTRUE, GPRC:$RFALSE))], s_cmov>;
 def CMOVLBS  : OForm4<  0x11, 0x14, "cmovlbs $RCOND,$RTRUE,$RDEST",
-                [(set GPRC:$RDEST, (select (and GPRC:$RCOND, 1), GPRC:$RTRUE, GPRC:$RFALSE))]>;
+                [(set GPRC:$RDEST, (select (and GPRC:$RCOND, 1), GPRC:$RTRUE, GPRC:$RFALSE))], s_cmov>;
 def CMOVEQ   : OForm4<  0x11, 0x24, "cmoveq $RCOND,$RTRUE,$RDEST",
-                [(set GPRC:$RDEST, (select (seteq GPRC:$RCOND, 0), GPRC:$RTRUE, GPRC:$RFALSE))]>;
+                [(set GPRC:$RDEST, (select (seteq GPRC:$RCOND, 0), GPRC:$RTRUE, GPRC:$RFALSE))], s_cmov>;
 def CMOVGE   : OForm4<  0x11, 0x46, "cmovge $RCOND,$RTRUE,$RDEST",
-                [(set GPRC:$RDEST, (select (setge GPRC:$RCOND, 0), GPRC:$RTRUE, GPRC:$RFALSE))]>;
+                [(set GPRC:$RDEST, (select (setge GPRC:$RCOND, 0), GPRC:$RTRUE, GPRC:$RFALSE))], s_cmov>;
 def CMOVGT   : OForm4<  0x11, 0x66, "cmovgt $RCOND,$RTRUE,$RDEST",
-                [(set GPRC:$RDEST, (select (setgt GPRC:$RCOND, 0), GPRC:$RTRUE, GPRC:$RFALSE))]>;
+                [(set GPRC:$RDEST, (select (setgt GPRC:$RCOND, 0), GPRC:$RTRUE, GPRC:$RFALSE))], s_cmov>;
 def CMOVLE   : OForm4<  0x11, 0x64, "cmovle $RCOND,$RTRUE,$RDEST",
-                [(set GPRC:$RDEST, (select (setle GPRC:$RCOND, 0), GPRC:$RTRUE, GPRC:$RFALSE))]>;
+                [(set GPRC:$RDEST, (select (setle GPRC:$RCOND, 0), GPRC:$RTRUE, GPRC:$RFALSE))], s_cmov>;
 def CMOVLT   : OForm4<  0x11, 0x44, "cmovlt $RCOND,$RTRUE,$RDEST",
-                [(set GPRC:$RDEST, (select (setlt GPRC:$RCOND, 0), GPRC:$RTRUE, GPRC:$RFALSE))]>;
+                [(set GPRC:$RDEST, (select (setlt GPRC:$RCOND, 0), GPRC:$RTRUE, GPRC:$RFALSE))], s_cmov>;
 def CMOVNE   : OForm4<  0x11, 0x26, "cmovne $RCOND,$RTRUE,$RDEST",
-                [(set GPRC:$RDEST, (select (setne GPRC:$RCOND, 0), GPRC:$RTRUE, GPRC:$RFALSE))]>;
+                [(set GPRC:$RDEST, (select (setne GPRC:$RCOND, 0), GPRC:$RTRUE, GPRC:$RFALSE))], s_cmov>;
 
 def CMOVEQi  : OForm4L< 0x11, 0x24, "cmoveq $RCOND,$RTRUE,$RDEST",
-                [(set GPRC:$RDEST, (select (setne GPRC:$RCOND, 0), GPRC:$RFALSE, immUExt8:$RTRUE))]>;
+                [(set GPRC:$RDEST, (select (setne GPRC:$RCOND, 0), GPRC:$RFALSE, immUExt8:$RTRUE))], s_cmov>;
 def CMOVGEi  : OForm4L< 0x11, 0x46, "cmovge $RCOND,$RTRUE,$RDEST",
-                [(set GPRC:$RDEST, (select (setlt GPRC:$RCOND, 0), GPRC:$RFALSE, immUExt8:$RTRUE))]>;
+                [(set GPRC:$RDEST, (select (setlt GPRC:$RCOND, 0), GPRC:$RFALSE, immUExt8:$RTRUE))], s_cmov>;
 def CMOVGTi  : OForm4L< 0x11, 0x66, "cmovgt $RCOND,$RTRUE,$RDEST",
-                [(set GPRC:$RDEST, (select (setle GPRC:$RCOND, 0), GPRC:$RFALSE, immUExt8:$RTRUE))]>;
+                [(set GPRC:$RDEST, (select (setle GPRC:$RCOND, 0), GPRC:$RFALSE, immUExt8:$RTRUE))], s_cmov>;
 def CMOVLEi  : OForm4L< 0x11, 0x64, "cmovle $RCOND,$RTRUE,$RDEST",
-                [(set GPRC:$RDEST, (select (setgt GPRC:$RCOND, 0), GPRC:$RFALSE, immUExt8:$RTRUE))]>;
+                [(set GPRC:$RDEST, (select (setgt GPRC:$RCOND, 0), GPRC:$RFALSE, immUExt8:$RTRUE))], s_cmov>;
 def CMOVLTi  : OForm4L< 0x11, 0x44, "cmovlt $RCOND,$RTRUE,$RDEST",
-                [(set GPRC:$RDEST, (select (setge GPRC:$RCOND, 0), GPRC:$RFALSE, immUExt8:$RTRUE))]>;
+                [(set GPRC:$RDEST, (select (setge GPRC:$RCOND, 0), GPRC:$RFALSE, immUExt8:$RTRUE))], s_cmov>;
 def CMOVNEi  : OForm4L< 0x11, 0x26, "cmovne $RCOND,$RTRUE,$RDEST",
-                [(set GPRC:$RDEST, (select (seteq GPRC:$RCOND, 0), GPRC:$RFALSE, immUExt8:$RTRUE))]>;
+                [(set GPRC:$RDEST, (select (seteq GPRC:$RCOND, 0), GPRC:$RFALSE, immUExt8:$RTRUE))], s_cmov>;
 def CMOVLBCi : OForm4L< 0x11, 0x16, "cmovlbc $RCOND,$RTRUE,$RDEST",
-                [(set GPRC:$RDEST, (select (and GPRC:$RCOND, 1), GPRC:$RFALSE, immUExt8:$RTRUE))]>;
+                [(set GPRC:$RDEST, (select (and GPRC:$RCOND, 1), GPRC:$RFALSE, immUExt8:$RTRUE))], s_cmov>;
 def CMOVLBSi : OForm4L< 0x11, 0x14, "cmovlbs $RCOND,$RTRUE,$RDEST",
-                [(set GPRC:$RDEST, (select (xor GPRC:$RCOND, 1), GPRC:$RFALSE, immUExt8:$RTRUE))]>;
+                [(set GPRC:$RDEST, (select (xor GPRC:$RCOND, 1), GPRC:$RFALSE, immUExt8:$RTRUE))], s_cmov>;
 
 
 //General pattern for cmov
@@ -166,41 +166,41 @@ def : Pat<(select GPRC:$which, GPRC:$src1, immUExt8:$src2),
 
 
 def ADDL     : OForm< 0x10, 0x00, "addl $RA,$RB,$RC",
-                      [(set GPRC:$RC, (intop (add GPRC:$RA, GPRC:$RB)))]>;
+                      [(set GPRC:$RC, (intop (add GPRC:$RA, GPRC:$RB)))], s_iadd>;
 def ADDLi    : OFormL<0x10, 0x00, "addl $RA,$L,$RC",
-                      [(set GPRC:$RC, (intop (add GPRC:$RA, immUExt8:$L)))]>;
+                      [(set GPRC:$RC, (intop (add GPRC:$RA, immUExt8:$L)))], s_iadd>;
 def ADDQ     : OForm< 0x10, 0x20, "addq $RA,$RB,$RC",
-                      [(set GPRC:$RC, (add GPRC:$RA, GPRC:$RB))]>;
+                      [(set GPRC:$RC, (add GPRC:$RA, GPRC:$RB))], s_iadd>;
 def ADDQi    : OFormL<0x10, 0x20, "addq $RA,$L,$RC",
-                      [(set GPRC:$RC, (add GPRC:$RA, immUExt8:$L))]>;
+                      [(set GPRC:$RC, (add GPRC:$RA, immUExt8:$L))], s_iadd>;
 def AND      : OForm< 0x11, 0x00, "and $RA,$RB,$RC",
-                      [(set GPRC:$RC, (and GPRC:$RA, GPRC:$RB))]>;
+                      [(set GPRC:$RC, (and GPRC:$RA, GPRC:$RB))], s_ilog>;
 def ANDi     : OFormL<0x11, 0x00, "and $RA,$L,$RC",
-                      [(set GPRC:$RC, (and GPRC:$RA, immUExt8:$L))]>;
+                      [(set GPRC:$RC, (and GPRC:$RA, immUExt8:$L))], s_ilog>;
 def BIC      : OForm< 0x11, 0x08, "bic $RA,$RB,$RC",
-                      [(set GPRC:$RC, (and GPRC:$RA, (not GPRC:$RB)))]>;
+                      [(set GPRC:$RC, (and GPRC:$RA, (not GPRC:$RB)))], s_ilog>;
 def BICi     : OFormL<0x11, 0x08, "bic $RA,$L,$RC", 
-                      [(set GPRC:$RC, (and GPRC:$RA, immUExt8inv:$L))]>;
+                      [(set GPRC:$RC, (and GPRC:$RA, immUExt8inv:$L))], s_ilog>;
 def BIS      : OForm< 0x11, 0x20, "bis $RA,$RB,$RC",
-                      [(set GPRC:$RC, (or GPRC:$RA, GPRC:$RB))]>;
+                      [(set GPRC:$RC, (or GPRC:$RA, GPRC:$RB))], s_ilog>;
 def BISi     : OFormL<0x11, 0x20, "bis $RA,$L,$RC",
-                      [(set GPRC:$RC, (or GPRC:$RA, immUExt8:$L))]>;
+                      [(set GPRC:$RC, (or GPRC:$RA, immUExt8:$L))], s_ilog>;
 def CTLZ     : OForm2<0x1C, 0x32, "CTLZ $RB,$RC", 
-                      [(set GPRC:$RC, (ctlz GPRC:$RB))]>;
+                      [(set GPRC:$RC, (ctlz GPRC:$RB))], s_imisc>;
 def CTPOP    : OForm2<0x1C, 0x30, "CTPOP $RB,$RC", 
-                      [(set GPRC:$RC, (ctpop GPRC:$RB))]>;
+                      [(set GPRC:$RC, (ctpop GPRC:$RB))], s_imisc>;
 def CTTZ     : OForm2<0x1C, 0x33, "CTTZ $RB,$RC", 
-                      [(set GPRC:$RC, (cttz GPRC:$RB))]>;
+                      [(set GPRC:$RC, (cttz GPRC:$RB))], s_imisc>;
 def EQV      : OForm< 0x11, 0x48, "eqv $RA,$RB,$RC",
-                      [(set GPRC:$RC, (xor GPRC:$RA, (not GPRC:$RB)))]>;
+                      [(set GPRC:$RC, (xor GPRC:$RA, (not GPRC:$RB)))], s_ilog>;
 def EQVi     : OFormL<0x11, 0x48, "eqv $RA,$L,$RC", 
-                      [(set GPRC:$RC, (xor GPRC:$RA, immUExt8inv:$L))]>;
+                      [(set GPRC:$RC, (xor GPRC:$RA, immUExt8inv:$L))], s_ilog>;
 def EXTBL    : OForm< 0x12, 0x06, "EXTBL $RA,$RB,$RC", 
-                      [(set GPRC:$RC, (and (srl GPRC:$RA, (shl GPRC:$RB, 3)), 255))]>;
+                      [(set GPRC:$RC, (and (srl GPRC:$RA, (shl GPRC:$RB, 3)), 255))], s_ishf>;
 def EXTWL    : OForm< 0x12, 0x16, "EXTWL $RA,$RB,$RC", 
-                      [(set GPRC:$RC, (and (srl GPRC:$RA, (shl GPRC:$RB, 3)), 65535))]>;
+                      [(set GPRC:$RC, (and (srl GPRC:$RA, (shl GPRC:$RB, 3)), 65535))], s_ishf>;
 def EXTLL    : OForm< 0x12, 0x26, "EXTLL $RA,$RB,$RC", 
-                      [(set GPRC:$RC, (and (srl GPRC:$RA, (shl GPRC:$RB, 3)), 4294967295))]>;
+                      [(set GPRC:$RC, (and (srl GPRC:$RA, (shl GPRC:$RB, 3)), 4294967295))], s_ishf>;
 
 //def EXTBLi   : OFormL<0x12, 0x06, "EXTBL $RA,$L,$RC", []>; //Extract byte low
 //def EXTLH    : OForm< 0x12, 0x6A, "EXTLH $RA,$RB,$RC", []>; //Extract longword high
@@ -246,116 +246,116 @@ def EXTLL    : OForm< 0x12, 0x26, "EXTLL $RA,$RB,$RC",
 //def MSKWLi   : OFormL<0x12, 0x12, "MSKWL $RA,$L,$RC", []>; //Mask word low
 
 def MULL     : OForm< 0x13, 0x00, "mull $RA,$RB,$RC",
-                      [(set GPRC:$RC, (intop (mul GPRC:$RA, GPRC:$RB)))]>;
+                      [(set GPRC:$RC, (intop (mul GPRC:$RA, GPRC:$RB)))], s_imul>;
 def MULLi    : OFormL<0x13, 0x00, "mull $RA,$L,$RC",
-                      [(set GPRC:$RC, (intop (mul GPRC:$RA, immUExt8:$L)))]>;
+                      [(set GPRC:$RC, (intop (mul GPRC:$RA, immUExt8:$L)))], s_imul>;
 def MULQ     : OForm< 0x13, 0x20, "mulq $RA,$RB,$RC",
-                      [(set GPRC:$RC, (mul GPRC:$RA, GPRC:$RB))]>;
+                      [(set GPRC:$RC, (mul GPRC:$RA, GPRC:$RB))], s_imul>;
 def MULQi    : OFormL<0x13, 0x20, "mulq $RA,$L,$RC",
-                      [(set GPRC:$RC, (mul GPRC:$RA, immUExt8:$L))]>;
+                      [(set GPRC:$RC, (mul GPRC:$RA, immUExt8:$L))], s_imul>;
 def ORNOT    : OForm< 0x11, 0x28, "ornot $RA,$RB,$RC",
-                      [(set GPRC:$RC, (or GPRC:$RA, (not GPRC:$RB)))]>;
+                      [(set GPRC:$RC, (or GPRC:$RA, (not GPRC:$RB)))], s_ilog>;
 def ORNOTi   : OFormL<0x11, 0x28, "ornot $RA,$L,$RC", 
-                      [(set GPRC:$RC, (or GPRC:$RA, immUExt8inv:$L))]>;
+                      [(set GPRC:$RC, (or GPRC:$RA, immUExt8inv:$L))], s_ilog>;
 def S4ADDL   : OForm< 0x10, 0x02, "s4addl $RA,$RB,$RC", 
-                      [(set GPRC:$RC, (intop (add4 GPRC:$RA, GPRC:$RB)))]>;
+                      [(set GPRC:$RC, (intop (add4 GPRC:$RA, GPRC:$RB)))], s_iadd>;
 def S4ADDLi  : OFormL<0x10, 0x02, "s4addl $RA,$L,$RC", 
-                      [(set GPRC:$RC, (intop (add4 GPRC:$RA, immUExt8:$L)))]>;
+                      [(set GPRC:$RC, (intop (add4 GPRC:$RA, immUExt8:$L)))], s_iadd>;
 def S4ADDQ   : OForm< 0x10, 0x22, "s4addq $RA,$RB,$RC", 
-                      [(set GPRC:$RC, (add4 GPRC:$RA, GPRC:$RB))]>;
+                      [(set GPRC:$RC, (add4 GPRC:$RA, GPRC:$RB))], s_iadd>;
 def S4ADDQi  : OFormL<0x10, 0x22, "s4addq $RA,$L,$RC", 
-                      [(set GPRC:$RC, (add4 GPRC:$RA, immUExt8:$L))]>;
+                      [(set GPRC:$RC, (add4 GPRC:$RA, immUExt8:$L))], s_iadd>;
 def S4SUBL   : OForm< 0x10, 0x0B, "s4subl $RA,$RB,$RC",
-                      [(set GPRC:$RC, (intop (sub4 GPRC:$RA, GPRC:$RB)))]>;
+                      [(set GPRC:$RC, (intop (sub4 GPRC:$RA, GPRC:$RB)))], s_iadd>;
 def S4SUBLi  : OFormL<0x10, 0x0B, "s4subl $RA,$L,$RC",
-                      [(set GPRC:$RC, (intop (sub4 GPRC:$RA, immUExt8:$L)))]>;
+                      [(set GPRC:$RC, (intop (sub4 GPRC:$RA, immUExt8:$L)))], s_iadd>;
 def S4SUBQ   : OForm< 0x10, 0x2B, "s4subq $RA,$RB,$RC", 
-                      [(set GPRC:$RC, (sub4 GPRC:$RA, GPRC:$RB))]>;
+                      [(set GPRC:$RC, (sub4 GPRC:$RA, GPRC:$RB))], s_iadd>;
 def S4SUBQi  : OFormL<0x10, 0x2B, "s4subq $RA,$L,$RC", 
-                      [(set GPRC:$RC, (sub4 GPRC:$RA, immUExt8:$L))]>;
+                      [(set GPRC:$RC, (sub4 GPRC:$RA, immUExt8:$L))], s_iadd>;
 def S8ADDL   : OForm< 0x10, 0x12, "s8addl $RA,$RB,$RC", 
-                      [(set GPRC:$RC, (intop (add8 GPRC:$RA, GPRC:$RB)))]>;
+                      [(set GPRC:$RC, (intop (add8 GPRC:$RA, GPRC:$RB)))], s_iadd>;
 def S8ADDLi  : OFormL<0x10, 0x12, "s8addl $RA,$L,$RC", 
-                      [(set GPRC:$RC, (intop (add8 GPRC:$RA, immUExt8:$L)))]>;
+                      [(set GPRC:$RC, (intop (add8 GPRC:$RA, immUExt8:$L)))], s_iadd>;
 def S8ADDQ   : OForm< 0x10, 0x32, "s8addq $RA,$RB,$RC", 
-                      [(set GPRC:$RC, (add8 GPRC:$RA, GPRC:$RB))]>;
+                      [(set GPRC:$RC, (add8 GPRC:$RA, GPRC:$RB))], s_iadd>;
 def S8ADDQi  : OFormL<0x10, 0x32, "s8addq $RA,$L,$RC", 
-                      [(set GPRC:$RC, (add8 GPRC:$RA, immUExt8:$L))]>;
+                      [(set GPRC:$RC, (add8 GPRC:$RA, immUExt8:$L))], s_iadd>;
 def S8SUBL   : OForm< 0x10, 0x1B, "s8subl $RA,$RB,$RC", 
-                      [(set GPRC:$RC, (intop (sub8 GPRC:$RA, GPRC:$RB)))]>;
+                      [(set GPRC:$RC, (intop (sub8 GPRC:$RA, GPRC:$RB)))], s_iadd>;
 def S8SUBLi  : OFormL<0x10, 0x1B, "s8subl $RA,$L,$RC", 
-                      [(set GPRC:$RC, (intop (add8 GPRC:$RA, immUExt8neg:$L)))]>;
+                      [(set GPRC:$RC, (intop (add8 GPRC:$RA, immUExt8neg:$L)))], s_iadd>;
 def S8SUBQ   : OForm< 0x10, 0x3B, "s8subq $RA,$RB,$RC", 
-                      [(set GPRC:$RC, (sub8 GPRC:$RA, GPRC:$RB))]>;
+                      [(set GPRC:$RC, (sub8 GPRC:$RA, GPRC:$RB))], s_iadd>;
 def S8SUBQi  : OFormL<0x10, 0x3B, "s8subq $RA,$L,$RC", 
-                      [(set GPRC:$RC, (add8 GPRC:$RA, immUExt8neg:$L))]>;
+                      [(set GPRC:$RC, (add8 GPRC:$RA, immUExt8neg:$L))], s_iadd>;
 def SEXTB    : OForm2<0x1C, 0x00, "sextb $RB,$RC", 
-                      [(set GPRC:$RC, (sext_inreg GPRC:$RB, i8))]>;
+                      [(set GPRC:$RC, (sext_inreg GPRC:$RB, i8))], s_ishf>;
 def SEXTW    : OForm2<0x1C, 0x01, "sextw $RB,$RC", 
-                      [(set GPRC:$RC, (sext_inreg GPRC:$RB, i16))]>;
+                      [(set GPRC:$RC, (sext_inreg GPRC:$RB, i16))], s_ishf>;
 def SL       : OForm< 0x12, 0x39, "sll $RA,$RB,$RC",
-                      [(set GPRC:$RC, (shl GPRC:$RA, GPRC:$RB))]>;
+                      [(set GPRC:$RC, (shl GPRC:$RA, GPRC:$RB))], s_ishf>;
 def SLi      : OFormL<0x12, 0x39, "sll $RA,$L,$RC",
-                      [(set GPRC:$RC, (shl GPRC:$RA, immUExt8:$L))]>;
+                      [(set GPRC:$RC, (shl GPRC:$RA, immUExt8:$L))], s_ishf>;
 def SRA      : OForm< 0x12, 0x3C, "sra $RA,$RB,$RC",
-                      [(set GPRC:$RC, (sra GPRC:$RA, GPRC:$RB))]>;
+                      [(set GPRC:$RC, (sra GPRC:$RA, GPRC:$RB))], s_ishf>;
 def SRAi     : OFormL<0x12, 0x3C, "sra $RA,$L,$RC",
-                      [(set GPRC:$RC, (sra GPRC:$RA, immUExt8:$L))]>;
+                      [(set GPRC:$RC, (sra GPRC:$RA, immUExt8:$L))], s_ishf>;
 def SRL      : OForm< 0x12, 0x34, "srl $RA,$RB,$RC",
-                      [(set GPRC:$RC, (srl GPRC:$RA, GPRC:$RB))]>;
+                      [(set GPRC:$RC, (srl GPRC:$RA, GPRC:$RB))], s_ishf>;
 def SRLi     : OFormL<0x12, 0x34, "srl $RA,$L,$RC",
-                      [(set GPRC:$RC, (srl GPRC:$RA, immUExt8:$L))]>;
+                      [(set GPRC:$RC, (srl GPRC:$RA, immUExt8:$L))], s_ishf>;
 def SUBL     : OForm< 0x10, 0x09, "subl $RA,$RB,$RC",
-                      [(set GPRC:$RC, (intop (sub GPRC:$RA, GPRC:$RB)))]>;
+                      [(set GPRC:$RC, (intop (sub GPRC:$RA, GPRC:$RB)))], s_iadd>;
 def SUBLi    : OFormL<0x10, 0x09, "subl $RA,$L,$RC",
-                      [(set GPRC:$RC, (intop (add GPRC:$RA, immUExt8neg:$L)))]>;
+                      [(set GPRC:$RC, (intop (add GPRC:$RA, immUExt8neg:$L)))], s_iadd>;
 def SUBQ     : OForm< 0x10, 0x29, "subq $RA,$RB,$RC",
-                      [(set GPRC:$RC, (sub GPRC:$RA, GPRC:$RB))]>;
+                      [(set GPRC:$RC, (sub GPRC:$RA, GPRC:$RB))], s_iadd>;
 def SUBQi    : OFormL<0x10, 0x29, "subq $RA,$L,$RC",
-                      [(set GPRC:$RC, (add GPRC:$RA, immUExt8neg:$L))]>;
+                      [(set GPRC:$RC, (add GPRC:$RA, immUExt8neg:$L))], s_iadd>;
 def UMULH    : OForm< 0x13, 0x30, "umulh $RA,$RB,$RC",
-                      [(set GPRC:$RC, (mulhu GPRC:$RA, GPRC:$RB))]>;                     
+                      [(set GPRC:$RC, (mulhu GPRC:$RA, GPRC:$RB))], s_imul>;                     
 def UMULHi   : OFormL<0x13, 0x30, "umulh $RA,$L,$RC", 
-                      [(set GPRC:$RC, (mulhu GPRC:$RA, immUExt8:$L))]>;
+                      [(set GPRC:$RC, (mulhu GPRC:$RA, immUExt8:$L))], s_imul>;
 def XOR      : OForm< 0x11, 0x40, "xor $RA,$RB,$RC",
-                      [(set GPRC:$RC, (xor GPRC:$RA, GPRC:$RB))]>;
+                      [(set GPRC:$RC, (xor GPRC:$RA, GPRC:$RB))], s_ilog>;
 def XORi     : OFormL<0x11, 0x40, "xor $RA,$L,$RC",
-                      [(set GPRC:$RC, (xor GPRC:$RA, immUExt8:$L))]>;
+                      [(set GPRC:$RC, (xor GPRC:$RA, immUExt8:$L))], s_ilog>;
 //FIXME: what to do about zap? the cases it catches are very complex
-def ZAP      : OForm< 0x12, 0x30, "zap $RA,$RB,$RC", []>; //Zero bytes
+def ZAP      : OForm< 0x12, 0x30, "zap $RA,$RB,$RC", [], s_ishf>; //Zero bytes
 //ZAPi is useless give ZAPNOTi
-def ZAPi     : OFormL<0x12, 0x30, "zap $RA,$L,$RC", []>; //Zero bytes
+def ZAPi     : OFormL<0x12, 0x30, "zap $RA,$L,$RC", [], s_ishf>; //Zero bytes
 //FIXME: what to do about zapnot? see ZAP :)
-def ZAPNOT   : OForm< 0x12, 0x31, "zapnot $RA,$RB,$RC", []>; //Zero bytes not
+def ZAPNOT   : OForm< 0x12, 0x31, "zapnot $RA,$RB,$RC", [], s_ishf>; //Zero bytes not
 def ZAPNOTi  : OFormL<0x12, 0x31, "zapnot $RA,$L,$RC", 
-                      [(set GPRC:$RC, (and GPRC:$RA, immZAP:$L))]>; 
+                      [(set GPRC:$RC, (and GPRC:$RA, immZAP:$L))], s_ishf>; 
 
 //Comparison, int
 //So this is a waste of what this instruction can do, but it still saves something
 def CMPBGE  : OForm< 0x10, 0x0F, "cmpbge $RA,$RB,$RC", 
-                     [(set GPRC:$RC, (setuge (and GPRC:$RA, 255), (and GPRC:$RB, 255)))]>;
+                     [(set GPRC:$RC, (setuge (and GPRC:$RA, 255), (and GPRC:$RB, 255)))], s_ilog>;
 def CMPBGEi : OFormL<0x10, 0x0F, "cmpbge $RA,$L,$RC",
-                     [(set GPRC:$RC, (setuge (and GPRC:$RA, 255), immUExt8:$L))]>;
+                     [(set GPRC:$RC, (setuge (and GPRC:$RA, 255), immUExt8:$L))], s_ilog>;
 def CMPEQ   : OForm< 0x10, 0x2D, "cmpeq $RA,$RB,$RC", 
-                     [(set GPRC:$RC, (seteq GPRC:$RA, GPRC:$RB))]>;
+                     [(set GPRC:$RC, (seteq GPRC:$RA, GPRC:$RB))], s_iadd>;
 def CMPEQi  : OFormL<0x10, 0x2D, "cmpeq $RA,$L,$RC", 
-                     [(set GPRC:$RC, (seteq GPRC:$RA, immUExt8:$L))]>;
+                     [(set GPRC:$RC, (seteq GPRC:$RA, immUExt8:$L))], s_iadd>;
 def CMPLE   : OForm< 0x10, 0x6D, "cmple $RA,$RB,$RC", 
-                     [(set GPRC:$RC, (setle GPRC:$RA, GPRC:$RB))]>;
+                     [(set GPRC:$RC, (setle GPRC:$RA, GPRC:$RB))], s_iadd>;
 def CMPLEi  : OFormL<0x10, 0x6D, "cmple $RA,$L,$RC",
-                     [(set GPRC:$RC, (setle GPRC:$RA, immUExt8:$L))]>;
+                     [(set GPRC:$RC, (setle GPRC:$RA, immUExt8:$L))], s_iadd>;
 def CMPLT   : OForm< 0x10, 0x4D, "cmplt $RA,$RB,$RC",
-                     [(set GPRC:$RC, (setlt GPRC:$RA, GPRC:$RB))]>;
+                     [(set GPRC:$RC, (setlt GPRC:$RA, GPRC:$RB))], s_iadd>;
 def CMPLTi  : OFormL<0x10, 0x4D, "cmplt $RA,$L,$RC",
-                     [(set GPRC:$RC, (setlt GPRC:$RA, immUExt8:$L))]>;
+                     [(set GPRC:$RC, (setlt GPRC:$RA, immUExt8:$L))], s_iadd>;
 def CMPULE  : OForm< 0x10, 0x3D, "cmpule $RA,$RB,$RC",
-                     [(set GPRC:$RC, (setule GPRC:$RA, GPRC:$RB))]>;
+                     [(set GPRC:$RC, (setule GPRC:$RA, GPRC:$RB))], s_iadd>;
 def CMPULEi : OFormL<0x10, 0x3D, "cmpule $RA,$L,$RC",
-                     [(set GPRC:$RC, (setule GPRC:$RA, immUExt8:$L))]>;
+                     [(set GPRC:$RC, (setule GPRC:$RA, immUExt8:$L))], s_iadd>;
 def CMPULT  : OForm< 0x10, 0x1D, "cmpult $RA,$RB,$RC",
-                     [(set GPRC:$RC, (setult GPRC:$RA, GPRC:$RB))]>;
+                     [(set GPRC:$RC, (setult GPRC:$RA, GPRC:$RB))], s_iadd>;
 def CMPULTi : OFormL<0x10, 0x1D, "cmpult $RA,$L,$RC", 
-                      [(set GPRC:$RC, (setult GPRC:$RA, immUExt8:$L))]>;
+                      [(set GPRC:$RC, (setult GPRC:$RA, immUExt8:$L))], s_iadd>;
 
 //Patterns for unsupported int comparisons
 def : Pat<(setueq GPRC:$X, GPRC:$Y), (CMPEQ GPRC:$X, GPRC:$Y)>;
@@ -381,16 +381,16 @@ def : Pat<(setune GPRC:$X, immUExt8:$Y), (CMPEQi (CMPEQ GPRC:$X, immUExt8:$Y), 0
 
 
 let isReturn = 1, isTerminator = 1, noResults = 1, Ra = 31, Rb = 26, disp = 1, Uses = [R26] in 
-  def RETDAG : MbrForm< 0x1A, 0x02, (ops), "ret $$31,($$26),1">; //Return from subroutine
+  def RETDAG : MbrForm< 0x1A, 0x02, (ops), "ret $$31,($$26),1", s_jsr>; //Return from subroutine
 
-def JMP : MbrForm< 0x1A, 0x00, (ops GPRC:$RD, GPRC:$RS, GPRC:$DISP), "jmp $RD,($RS),$DISP">; //Jump
+def JMP : MbrForm< 0x1A, 0x00, (ops GPRC:$RD, GPRC:$RS, GPRC:$DISP), "jmp $RD,($RS),$DISP", s_jsr>; //Jump
 let isCall = 1, noResults = 1, Ra = 26,
     Defs = [R0, R1, R2, R3, R4, R5, R6, R7, R8, R16, R17, R18, R19,
             R20, R21, R22, R23, R24, R25, R26, R27, R28, R29,
             F0, F1,
             F10, F11, F12, F13, F14, F15, F16, F17, F18, F19,
             F20, F21, F22, F23, F24, F25, F26, F27, F28, F29, F30], Uses = [R29] in {
-    def BSR : BFormD<0x34, "bsr $$26,$$$DISP..ng", []>; //Branch to subroutine
+    def BSR : BFormD<0x34, "bsr $$26,$$$DISP..ng", [], s_jsr>; //Branch to subroutine
 }
 let isCall = 1, noResults = 1, Ra = 26, Rb = 27, disp = 0,
     Defs = [R0, R1, R2, R3, R4, R5, R6, R7, R8, R16, R17, R18, R19,
@@ -398,80 +398,80 @@ let isCall = 1, noResults = 1, Ra = 26, Rb = 27, disp = 0,
             F0, F1,
             F10, F11, F12, F13, F14, F15, F16, F17, F18, F19,
             F20, F21, F22, F23, F24, F25, F26, F27, F28, F29, F30], Uses = [R27, R29] in {
-    def JSR : MbrForm< 0x1A, 0x01, (ops ), "jsr $$26,($$27),0">; //Jump to subroutine
+    def JSR : MbrForm< 0x1A, 0x01, (ops ), "jsr $$26,($$27),0", s_jsr>; //Jump to subroutine
 }
 
 let isCall = 1, noResults = 1, Ra = 23, Rb = 27, disp = 0,
     Defs = [R23, R24, R25, R27, R28], Uses = [R24, R25, R27] in
-  def JSRs : MbrForm< 0x1A, 0x01, (ops ), "jsr $$23,($$27),0">; //Jump to div or rem
+  def JSRs : MbrForm< 0x1A, 0x01, (ops ), "jsr $$23,($$27),0", s_jsr>; //Jump to div or rem
 
 
-def JSR_COROUTINE : MbrForm< 0x1A, 0x03, (ops GPRC:$RD, GPRC:$RS, s14imm:$DISP), "jsr_coroutine $RD,($RS),$DISP">; //Jump to subroutine return
+def JSR_COROUTINE : MbrForm< 0x1A, 0x03, (ops GPRC:$RD, GPRC:$RS, s14imm:$DISP), "jsr_coroutine $RD,($RS),$DISP", s_jsr>; //Jump to subroutine return
 
 let OperandList = (ops GPRC:$RA, s64imm:$DISP, GPRC:$RB) in {
 def LDQ   : MForm<0x29, 0, 1, "ldq $RA,$DISP($RB)",
-                 [(set GPRC:$RA, (load (add GPRC:$RB, immSExt16:$DISP)))]>;
+                 [(set GPRC:$RA, (load (add GPRC:$RB, immSExt16:$DISP)))], s_ild>;
 def LDQr  : MForm<0x29, 0, 1, "ldq $RA,$DISP($RB)\t\t!gprellow",
-                 [(set GPRC:$RA, (load (Alpha_gprello tglobaladdr:$DISP, GPRC:$RB)))]>;
+                 [(set GPRC:$RA, (load (Alpha_gprello tglobaladdr:$DISP, GPRC:$RB)))], s_ild>;
 def LDL   : MForm<0x28, 0, 1, "ldl $RA,$DISP($RB)",
-                 [(set GPRC:$RA, (sextload (add GPRC:$RB, immSExt16:$DISP), i32))]>;
+                 [(set GPRC:$RA, (sextload (add GPRC:$RB, immSExt16:$DISP), i32))], s_ild>;
 def LDLr  : MForm<0x28, 0, 1, "ldl $RA,$DISP($RB)\t\t!gprellow",
-                 [(set GPRC:$RA, (sextload (Alpha_gprello tglobaladdr:$DISP, GPRC:$RB), i32))]>;
+                 [(set GPRC:$RA, (sextload (Alpha_gprello tglobaladdr:$DISP, GPRC:$RB), i32))], s_ild>;
 def LDBU  : MForm<0x0A, 0, 1, "ldbu $RA,$DISP($RB)",
-                 [(set GPRC:$RA, (zextload (add GPRC:$RB, immSExt16:$DISP), i8))]>;
+                 [(set GPRC:$RA, (zextload (add GPRC:$RB, immSExt16:$DISP), i8))], s_ild>;
 def LDBUr : MForm<0x0A, 0, 1, "ldbu $RA,$DISP($RB)\t\t!gprellow",
-                 [(set GPRC:$RA, (zextload (Alpha_gprello tglobaladdr:$DISP, GPRC:$RB), i8))]>;
+                 [(set GPRC:$RA, (zextload (Alpha_gprello tglobaladdr:$DISP, GPRC:$RB), i8))], s_ild>;
 def LDWU  : MForm<0x0C, 0, 1, "ldwu $RA,$DISP($RB)",
-                 [(set GPRC:$RA, (zextload (add GPRC:$RB, immSExt16:$DISP), i16))]>;
+                 [(set GPRC:$RA, (zextload (add GPRC:$RB, immSExt16:$DISP), i16))], s_ild>;
 def LDWUr : MForm<0x0C, 0, 1, "ldwu $RA,$DISP($RB)\t\t!gprellow",
-                 [(set GPRC:$RA, (zextload (Alpha_gprello tglobaladdr:$DISP, GPRC:$RB), i16))]>;
+                 [(set GPRC:$RA, (zextload (Alpha_gprello tglobaladdr:$DISP, GPRC:$RB), i16))], s_ild>;
 def STB   : MForm<0x0E, 1, 0, "stb $RA,$DISP($RB)",
-		 [(truncstore GPRC:$RA, (add GPRC:$RB, immSExt16:$DISP), i8)]>;
+		 [(truncstore GPRC:$RA, (add GPRC:$RB, immSExt16:$DISP), i8)], s_ist>;
 def STBr  : MForm<0x0E, 1, 0, "stb $RA,$DISP($RB)\t\t!gprellow",
-		 [(truncstore GPRC:$RA, (Alpha_gprello tglobaladdr:$DISP, GPRC:$RB), i8)]>;
+		 [(truncstore GPRC:$RA, (Alpha_gprello tglobaladdr:$DISP, GPRC:$RB), i8)], s_ist>;
 def STW   : MForm<0x0D, 1, 0, "stw $RA,$DISP($RB)",
-		 [(truncstore GPRC:$RA, (add GPRC:$RB, immSExt16:$DISP), i16)]>;
+		 [(truncstore GPRC:$RA, (add GPRC:$RB, immSExt16:$DISP), i16)], s_ist>;
 def STWr  : MForm<0x0D, 1, 0, "stw $RA,$DISP($RB)\t\t!gprellow",
-		 [(truncstore GPRC:$RA, (Alpha_gprello tglobaladdr:$DISP, GPRC:$RB), i16)]>;
+		 [(truncstore GPRC:$RA, (Alpha_gprello tglobaladdr:$DISP, GPRC:$RB), i16)], s_ist>;
 def STL   : MForm<0x2C, 1, 0, "stl $RA,$DISP($RB)",
-		 [(truncstore GPRC:$RA, (add GPRC:$RB, immSExt16:$DISP), i32)]>;
+		 [(truncstore GPRC:$RA, (add GPRC:$RB, immSExt16:$DISP), i32)], s_ist>;
 def STLr  : MForm<0x2C, 1, 0, "stl $RA,$DISP($RB)\t\t!gprellow",
-		 [(truncstore GPRC:$RA, (Alpha_gprello tglobaladdr:$DISP, GPRC:$RB), i32)]>;
+		 [(truncstore GPRC:$RA, (Alpha_gprello tglobaladdr:$DISP, GPRC:$RB), i32)], s_ist>;
 def STQ   : MForm<0x2D, 1, 0, "stq $RA,$DISP($RB)",
-		 [(store GPRC:$RA, (add GPRC:$RB, immSExt16:$DISP))]>;
+		 [(store GPRC:$RA, (add GPRC:$RB, immSExt16:$DISP))], s_ist>;
 def STQr  : MForm<0x2D, 1, 0, "stq $RA,$DISP($RB)\t\t!gprellow",
-		 [(store GPRC:$RA, (Alpha_gprello tglobaladdr:$DISP, GPRC:$RB))]>;
+		 [(store GPRC:$RA, (Alpha_gprello tglobaladdr:$DISP, GPRC:$RB))], s_ist>;
 
 //Load address
 def LDA   : MForm<0x08, 0, 0, "lda $RA,$DISP($RB)",
-                 [(set GPRC:$RA, (add GPRC:$RB, immSExt16:$DISP))]>;
+                 [(set GPRC:$RA, (add GPRC:$RB, immSExt16:$DISP))], s_lda>;
 def LDAr  : MForm<0x08, 0, 0, "lda $RA,$DISP($RB)\t\t!gprellow",
-                 [(set GPRC:$RA, (Alpha_gprello tglobaladdr:$DISP, GPRC:$RB))]>;  //Load address
+                 [(set GPRC:$RA, (Alpha_gprello tglobaladdr:$DISP, GPRC:$RB))], s_lda>;  //Load address
 def LDAH  : MForm<0x09, 0, 0, "ldah $RA,$DISP($RB)",
-                 []>;  //Load address high
+                 [], s_lda>;  //Load address high
 def LDAHr : MForm<0x09, 0, 0, "ldah $RA,$DISP($RB)\t\t!gprelhigh",
-                 [(set GPRC:$RA, (Alpha_gprelhi tglobaladdr:$DISP, GPRC:$RB))]>;  //Load address high
+                 [(set GPRC:$RA, (Alpha_gprelhi tglobaladdr:$DISP, GPRC:$RB))], s_lda>;  //Load address high
 }
 
 let OperandList = (ops F4RC:$RA, s64imm:$DISP, GPRC:$RB) in {
 def STS  : MForm<0x26, 1, 0, "sts $RA,$DISP($RB)",
-		[(store F4RC:$RA, (add GPRC:$RB, immSExt16:$DISP))]>;
+		[(store F4RC:$RA, (add GPRC:$RB, immSExt16:$DISP))], s_fst>;
 def STSr : MForm<0x26, 1, 0, "sts $RA,$DISP($RB)\t\t!gprellow",
-		[(store F4RC:$RA, (Alpha_gprello tglobaladdr:$DISP, GPRC:$RB))]>;
+		[(store F4RC:$RA, (Alpha_gprello tglobaladdr:$DISP, GPRC:$RB))], s_fst>;
 def LDS  : MForm<0x22, 0, 1, "lds $RA,$DISP($RB)",
-		[(set F4RC:$RA, (load (add GPRC:$RB, immSExt16:$DISP)))]>;
+		[(set F4RC:$RA, (load (add GPRC:$RB, immSExt16:$DISP)))], s_fld>;
 def LDSr : MForm<0x22, 0, 1, "lds $RA,$DISP($RB)\t\t!gprellow",
-		[(set F4RC:$RA, (load (Alpha_gprello tglobaladdr:$DISP, GPRC:$RB)))]>;
+		[(set F4RC:$RA, (load (Alpha_gprello tglobaladdr:$DISP, GPRC:$RB)))], s_fld>;
 }
 let OperandList = (ops F8RC:$RA, s64imm:$DISP, GPRC:$RB) in {
 def STT  : MForm<0x27, 1, 0, "stt $RA,$DISP($RB)",
-		[(store F8RC:$RA, (add GPRC:$RB, immSExt16:$DISP))]>;
+		[(store F8RC:$RA, (add GPRC:$RB, immSExt16:$DISP))], s_fst>;
 def STTr : MForm<0x27, 1, 0, "stt $RA,$DISP($RB)\t\t!gprellow",
-		[(store F8RC:$RA, (Alpha_gprello tglobaladdr:$DISP, GPRC:$RB))]>;
+		[(store F8RC:$RA, (Alpha_gprello tglobaladdr:$DISP, GPRC:$RB))], s_fst>;
 def LDT  : MForm<0x23, 0, 1, "ldt $RA,$DISP($RB)",
-		[(set F8RC:$RA, (load (add GPRC:$RB, immSExt16:$DISP)))]>;
+		[(set F8RC:$RA, (load (add GPRC:$RB, immSExt16:$DISP)))], s_fld>;
 def LDTr : MForm<0x23, 0, 1, "ldt $RA,$DISP($RB)\t\t!gprellow",
-		[(set F8RC:$RA, (load (Alpha_gprello tglobaladdr:$DISP, GPRC:$RB)))]>;
+		[(set F8RC:$RA, (load (Alpha_gprello tglobaladdr:$DISP, GPRC:$RB)))], s_fld>;
 }
 
 
@@ -538,19 +538,19 @@ def : Pat<(truncstore GPRC:$DATA, GPRC:$addr, i8),
 
 //load address, rellocated gpdist form
 let OperandList = (ops GPRC:$RA, s16imm:$DISP, GPRC:$RB, s16imm:$NUM) in {
-def LDAg  : MForm<0x08, 0, 1, "lda $RA,0($RB)\t\t!gpdisp!$NUM", []>;  //Load address
-def LDAHg : MForm<0x09, 0, 1, "ldah $RA,0($RB)\t\t!gpdisp!$NUM", []>;  //Load address
+def LDAg  : MForm<0x08, 0, 1, "lda $RA,0($RB)\t\t!gpdisp!$NUM", [], s_lda>;  //Load address
+def LDAHg : MForm<0x09, 0, 1, "ldah $RA,0($RB)\t\t!gpdisp!$NUM", [], s_lda>;  //Load address
 }
 
 //Load quad, rellocated literal form
 let OperandList = (ops GPRC:$RA, s64imm:$DISP, GPRC:$RB) in 
 def LDQl : MForm<0x29, 0, 1, "ldq $RA,$DISP($RB)\t\t!literal",
-                 [(set GPRC:$RA, (Alpha_rellit tglobaladdr:$DISP, GPRC:$RB))]>;
+                 [(set GPRC:$RA, (Alpha_rellit tglobaladdr:$DISP, GPRC:$RB))], s_ild>;
 def : Pat<(Alpha_rellit texternalsym:$ext, GPRC:$RB),
           (LDQl texternalsym:$ext, GPRC:$RB)>;
 
 
-def RPCC : MfcForm<0x18, 0xC000, "rpcc $RA">; //Read process cycle counter
+def RPCC : MfcForm<0x18, 0xC000, "rpcc $RA", s_rpcc>; //Read process cycle counter
 
 //Basic Floating point ops
 
@@ -558,56 +558,56 @@ def RPCC : MfcForm<0x18, 0xC000, "rpcc $RA">; //Read process cycle counter
 
 let OperandList = (ops F4RC:$RC, F4RC:$RB), Fa = 31 in 
 def SQRTS : FPForm<0x14, 0x58B, "sqrts/su $RB,$RC",
-                   [(set F4RC:$RC, (fsqrt F4RC:$RB))]>;
+                   [(set F4RC:$RC, (fsqrt F4RC:$RB))], s_fsqrts>;
 
 let OperandList = (ops F4RC:$RC, F4RC:$RA, F4RC:$RB) in {
 def ADDS  : FPForm<0x16, 0x580, "adds/su $RA,$RB,$RC",
-                   [(set F4RC:$RC, (fadd F4RC:$RA, F4RC:$RB))]>;
+                   [(set F4RC:$RC, (fadd F4RC:$RA, F4RC:$RB))], s_fadd>;
 def SUBS  : FPForm<0x16, 0x581, "subs/su $RA,$RB,$RC",
-                   [(set F4RC:$RC, (fsub F4RC:$RA, F4RC:$RB))]>;
+                   [(set F4RC:$RC, (fsub F4RC:$RA, F4RC:$RB))], s_fadd>;
 def DIVS  : FPForm<0x16, 0x583, "divs/su $RA,$RB,$RC",
-                   [(set F4RC:$RC, (fdiv F4RC:$RA, F4RC:$RB))]>;
+                   [(set F4RC:$RC, (fdiv F4RC:$RA, F4RC:$RB))], s_fdivs>;
 def MULS  : FPForm<0x16, 0x582, "muls/su $RA,$RB,$RC",
-                   [(set F4RC:$RC, (fmul F4RC:$RA, F4RC:$RB))]>;
+                   [(set F4RC:$RC, (fmul F4RC:$RA, F4RC:$RB))], s_fmul>;
 
 def CPYSS  : FPForm<0x17, 0x020, "cpys $RA,$RB,$RC",
-                   [(set F4RC:$RC, (fcopysign F4RC:$RA, F4RC:$RB))]>;
-def CPYSES : FPForm<0x17, 0x022, "cpyse $RA,$RB,$RC",[]>; //Copy sign and exponent
+                   [(set F4RC:$RC, (fcopysign F4RC:$RA, F4RC:$RB))], s_fadd>;
+def CPYSES : FPForm<0x17, 0x022, "cpyse $RA,$RB,$RC",[], s_fadd>; //Copy sign and exponent
 //FIXME: This might be legalized in the oposite manner
 def CPYSNS : FPForm<0x17, 0x021, "cpysn $RA,$RB,$RC",
-                   [(set F4RC:$RC, (fneg (fcopysign F4RC:$RA, F4RC:$RB)))]>;
+                   [(set F4RC:$RC, (fneg (fcopysign F4RC:$RA, F4RC:$RB)))], s_fadd>;
 }
 
 //Doubles
 
 let OperandList = (ops F8RC:$RC, F8RC:$RB), Fa = 31 in 
 def SQRTT : FPForm<0x14, 0x5AB, "sqrtt/su $RB,$RC",
-                   [(set F8RC:$RC, (fsqrt F8RC:$RB))]>;
+                   [(set F8RC:$RC, (fsqrt F8RC:$RB))], s_fsqrtt>;
 
 let OperandList = (ops F8RC:$RC, F8RC:$RA, F8RC:$RB) in {
 def ADDT  : FPForm<0x16, 0x5A0, "addt/su $RA,$RB,$RC",
-                   [(set F8RC:$RC, (fadd F8RC:$RA, F8RC:$RB))]>;
+                   [(set F8RC:$RC, (fadd F8RC:$RA, F8RC:$RB))], s_fadd>;
 def SUBT  : FPForm<0x16, 0x5A1, "subt/su $RA,$RB,$RC",
-                   [(set F8RC:$RC, (fsub F8RC:$RA, F8RC:$RB))]>;
+                   [(set F8RC:$RC, (fsub F8RC:$RA, F8RC:$RB))], s_fadd>;
 def DIVT  : FPForm<0x16, 0x5A3, "divt/su $RA,$RB,$RC",
-                   [(set F8RC:$RC, (fdiv F8RC:$RA, F8RC:$RB))]>;
+                   [(set F8RC:$RC, (fdiv F8RC:$RA, F8RC:$RB))], s_fdivt>;
 def MULT  : FPForm<0x16, 0x5A2, "mult/su $RA,$RB,$RC",
-                   [(set F8RC:$RC, (fmul F8RC:$RA, F8RC:$RB))]>;
+                   [(set F8RC:$RC, (fmul F8RC:$RA, F8RC:$RB))], s_fmul>;
 
 def CPYST  : FPForm<0x17, 0x020, "cpys $RA,$RB,$RC",
-                   [(set F8RC:$RC, (fcopysign F8RC:$RA, F8RC:$RB))]>;
-def CPYSET : FPForm<0x17, 0x022, "cpyse $RA,$RB,$RC",[]>; //Copy sign and exponent
+                   [(set F8RC:$RC, (fcopysign F8RC:$RA, F8RC:$RB))], s_fadd>;
+def CPYSET : FPForm<0x17, 0x022, "cpyse $RA,$RB,$RC",[], s_fadd>; //Copy sign and exponent
 //FIXME: This might be legalized in the oposite manner
 def CPYSNT : FPForm<0x17, 0x021, "cpysn $RA,$RB,$RC",
-                   [(set F8RC:$RC, (fneg (fcopysign F8RC:$RA, F8RC:$RB)))]>;
+                   [(set F8RC:$RC, (fneg (fcopysign F8RC:$RA, F8RC:$RB)))], s_fadd>;
 
-def CMPTEQ : FPForm<0x16, 0x5A5, "cmpteq/su $RA,$RB,$RC", []>;
+def CMPTEQ : FPForm<0x16, 0x5A5, "cmpteq/su $RA,$RB,$RC", [], s_fadd>;
 //                    [(set F8RC:$RC, (seteq F8RC:$RA, F8RC:$RB))]>;
-def CMPTLE : FPForm<0x16, 0x5A7, "cmptle/su $RA,$RB,$RC", []>;
+def CMPTLE : FPForm<0x16, 0x5A7, "cmptle/su $RA,$RB,$RC", [], s_fadd>;
 //                    [(set F8RC:$RC, (setle F8RC:$RA, F8RC:$RB))]>;
-def CMPTLT : FPForm<0x16, 0x5A6, "cmptlt/su $RA,$RB,$RC", []>;
+def CMPTLT : FPForm<0x16, 0x5A6, "cmptlt/su $RA,$RB,$RC", [], s_fadd>;
 //                    [(set F8RC:$RC, (setlt F8RC:$RA, F8RC:$RB))]>;
-def CMPTUN : FPForm<0x16, 0x5A4, "cmptun/su $RA,$RB,$RC", []>;
+def CMPTUN : FPForm<0x16, 0x5A4, "cmptun/su $RA,$RB,$RC", [], s_fadd>;
 //                    [(set F8RC:$RC, (setuo F8RC:$RA, F8RC:$RB))]>;
 }
 //TODO: Add lots more FP patterns
@@ -615,22 +615,22 @@ def CMPTUN : FPForm<0x16, 0x5A4, "cmptun/su $RA,$RB,$RC", []>;
 //conditional moves, floats
 let OperandList = (ops F4RC:$RDEST, F4RC:$RFALSE, F4RC:$RTRUE, F8RC:$RCOND),
     isTwoAddress = 1 in {
-def FCMOVEQS : FPForm<0x17, 0x02A, "fcmoveq $RCOND,$RTRUE,$RDEST",[]>; //FCMOVE if = zero
-def FCMOVGES : FPForm<0x17, 0x02D, "fcmovge $RCOND,$RTRUE,$RDEST",[]>; //FCMOVE if >= zero
-def FCMOVGTS : FPForm<0x17, 0x02F, "fcmovgt $RCOND,$RTRUE,$RDEST",[]>; //FCMOVE if > zero
-def FCMOVLES : FPForm<0x17, 0x02E, "fcmovle $RCOND,$RTRUE,$RDEST",[]>; //FCMOVE if <= zero
-def FCMOVLTS : FPForm<0x17, 0x02C, "fcmovlt $RCOND,$RTRUE,$RDEST",[]>; // FCMOVE if < zero
-def FCMOVNES : FPForm<0x17, 0x02B, "fcmovne $RCOND,$RTRUE,$RDEST",[]>; //FCMOVE if != zero
+def FCMOVEQS : FPForm<0x17, 0x02A, "fcmoveq $RCOND,$RTRUE,$RDEST",[], s_fcmov>; //FCMOVE if = zero
+def FCMOVGES : FPForm<0x17, 0x02D, "fcmovge $RCOND,$RTRUE,$RDEST",[], s_fcmov>; //FCMOVE if >= zero
+def FCMOVGTS : FPForm<0x17, 0x02F, "fcmovgt $RCOND,$RTRUE,$RDEST",[], s_fcmov>; //FCMOVE if > zero
+def FCMOVLES : FPForm<0x17, 0x02E, "fcmovle $RCOND,$RTRUE,$RDEST",[], s_fcmov>; //FCMOVE if <= zero
+def FCMOVLTS : FPForm<0x17, 0x02C, "fcmovlt $RCOND,$RTRUE,$RDEST",[], s_fcmov>; // FCMOVE if < zero
+def FCMOVNES : FPForm<0x17, 0x02B, "fcmovne $RCOND,$RTRUE,$RDEST",[], s_fcmov>; //FCMOVE if != zero
 }
 //conditional moves, doubles
 let OperandList = (ops F8RC:$RDEST, F8RC:$RFALSE, F8RC:$RTRUE, F8RC:$RCOND),
     isTwoAddress = 1 in {
-def FCMOVEQT : FPForm<0x17, 0x02A, "fcmoveq $RCOND,$RTRUE,$RDEST", []>;
-def FCMOVGET : FPForm<0x17, 0x02D, "fcmovge $RCOND,$RTRUE,$RDEST", []>;
-def FCMOVGTT : FPForm<0x17, 0x02F, "fcmovgt $RCOND,$RTRUE,$RDEST", []>;
-def FCMOVLET : FPForm<0x17, 0x02E, "fcmovle $RCOND,$RTRUE,$RDEST", []>;
-def FCMOVLTT : FPForm<0x17, 0x02C, "fcmovlt $RCOND,$RTRUE,$RDEST", []>;
-def FCMOVNET : FPForm<0x17, 0x02B, "fcmovne $RCOND,$RTRUE,$RDEST", []>;
+def FCMOVEQT : FPForm<0x17, 0x02A, "fcmoveq $RCOND,$RTRUE,$RDEST", [], s_fcmov>;
+def FCMOVGET : FPForm<0x17, 0x02D, "fcmovge $RCOND,$RTRUE,$RDEST", [], s_fcmov>;
+def FCMOVGTT : FPForm<0x17, 0x02F, "fcmovgt $RCOND,$RTRUE,$RDEST", [], s_fcmov>;
+def FCMOVLET : FPForm<0x17, 0x02E, "fcmovle $RCOND,$RTRUE,$RDEST", [], s_fcmov>;
+def FCMOVLTT : FPForm<0x17, 0x02C, "fcmovlt $RCOND,$RTRUE,$RDEST", [], s_fcmov>;
+def FCMOVNET : FPForm<0x17, 0x02B, "fcmovne $RCOND,$RTRUE,$RDEST", [], s_fcmov>;
 }
 
 //misc FP selects
@@ -664,32 +664,32 @@ def : Pat<(select (setle F8RC:$RA, F8RC:$RB), F4RC:$st, F4RC:$sf),
 
 
 let OperandList = (ops GPRC:$RC, F4RC:$RA), Fb = 31 in 
-def FTOIS : FPForm<0x1C, 0x078, "ftois $RA,$RC",[]>; //Floating to integer move, S_floating
+def FTOIS : FPForm<0x1C, 0x078, "ftois $RA,$RC",[], s_ftoi>; //Floating to integer move, S_floating
 let OperandList = (ops GPRC:$RC, F8RC:$RA), Fb = 31 in 
 def FTOIT : FPForm<0x1C, 0x070, "ftoit $RA,$RC",
-        [(set GPRC:$RC, (Alpha_ftoit F8RC:$RA))]>; //Floating to integer move
+        [(set GPRC:$RC, (Alpha_ftoit F8RC:$RA))], s_ftoi>; //Floating to integer move
 let OperandList = (ops F4RC:$RC, GPRC:$RA), Fb = 31 in 
-def ITOFS : FPForm<0x14, 0x004, "itofs $RA,$RC",[]>; //Integer to floating move, S_floating
+def ITOFS : FPForm<0x14, 0x004, "itofs $RA,$RC",[], s_itof>; //Integer to floating move, S_floating
 let OperandList = (ops F8RC:$RC, GPRC:$RA), Fb = 31 in 
 def ITOFT : FPForm<0x14, 0x024, "itoft $RA,$RC",
-        [(set F8RC:$RC, (Alpha_itoft GPRC:$RA))]>; //Integer to floating move
+        [(set F8RC:$RC, (Alpha_itoft GPRC:$RA))], s_itof>; //Integer to floating move
 
 
 let OperandList = (ops F4RC:$RC, F8RC:$RB), Fa = 31 in 
 def CVTQS : FPForm<0x16, 0x7BC, "cvtqs/sui $RB,$RC",
-        [(set F4RC:$RC, (Alpha_cvtqs F8RC:$RB))]>;
+        [(set F4RC:$RC, (Alpha_cvtqs F8RC:$RB))], s_fadd>;
 let OperandList = (ops F8RC:$RC, F8RC:$RB), Fa = 31 in 
 def CVTQT : FPForm<0x16, 0x7BE, "cvtqt/sui $RB,$RC",
-        [(set F8RC:$RC, (Alpha_cvtqt F8RC:$RB))]>;
+        [(set F8RC:$RC, (Alpha_cvtqt F8RC:$RB))], s_fadd>;
 let OperandList = (ops F8RC:$RC, F8RC:$RB), Fa = 31 in 
 def CVTTQ : FPForm<0x16, 0x52F, "cvttq/svc $RB,$RC",
-        [(set F8RC:$RC, (Alpha_cvttq F8RC:$RB))]>;
+        [(set F8RC:$RC, (Alpha_cvttq F8RC:$RB))], s_fadd>;
 let OperandList = (ops F8RC:$RC, F4RC:$RB), Fa = 31 in 
 def CVTST : FPForm<0x16, 0x6AC, "cvtst/s $RB,$RC",
-                   [(set F8RC:$RC, (fextend F4RC:$RB))]>;
+                   [(set F8RC:$RC, (fextend F4RC:$RB))], s_fadd>;
 let OperandList = (ops F4RC:$RC, F8RC:$RB), Fa = 31 in 
 def CVTTS : FPForm<0x16, 0x7AC, "cvtts/sui $RB,$RC",
-                   [(set F4RC:$RC, (fround F8RC:$RB))]>;
+                   [(set F4RC:$RC, (fround F8RC:$RB))], s_fadd>;
 
 
 /////////////////////////////////////////////////////////
@@ -697,38 +697,38 @@ def CVTTS : FPForm<0x16, 0x7AC, "cvtts/sui $RB,$RC",
 /////////////////////////////////////////////////////////
 let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, noResults = 1 in {
 let Ra = 31 in
-def BR : BFormD<0x30, "br $$31,$DISP", [(br bb:$DISP)]>;
+def BR : BFormD<0x30, "br $$31,$DISP", [(br bb:$DISP)], s_ubr>;
 
 //Branches, int
 def BEQ  : BForm<0x39, "beq $RA,$DISP", 
-                 [(brcond (seteq GPRC:$RA, 0), bb:$DISP)]>;
+                 [(brcond (seteq GPRC:$RA, 0), bb:$DISP)], s_icbr>;
 def BGE  : BForm<0x3E, "bge $RA,$DISP", 
-                 [(brcond (setge GPRC:$RA, 0), bb:$DISP)]>;
+                 [(brcond (setge GPRC:$RA, 0), bb:$DISP)], s_icbr>;
 def BGT  : BForm<0x3F, "bgt $RA,$DISP",
-                 [(brcond (setgt GPRC:$RA, 0), bb:$DISP)]>;
-def BLBC : BForm<0x38, "blbc $RA,$DISP", []>; //TODO: Low bit clear
+                 [(brcond (setgt GPRC:$RA, 0), bb:$DISP)], s_icbr>;
+def BLBC : BForm<0x38, "blbc $RA,$DISP", [], s_icbr>; //TODO: Low bit clear
 def BLBS : BForm<0x3C, "blbs $RA,$DISP",
-                 [(brcond (and GPRC:$RA, 1), bb:$DISP)]>;
+                 [(brcond (and GPRC:$RA, 1), bb:$DISP)], s_icbr>;
 def BLE  : BForm<0x3B, "ble $RA,$DISP",
-                 [(brcond (setle GPRC:$RA, 0), bb:$DISP)]>;
+                 [(brcond (setle GPRC:$RA, 0), bb:$DISP)], s_icbr>;
 def BLT  : BForm<0x3A, "blt $RA,$DISP",
-                 [(brcond (setlt GPRC:$RA, 0), bb:$DISP)]>;
+                 [(brcond (setlt GPRC:$RA, 0), bb:$DISP)], s_icbr>;
 def BNE  : BForm<0x3D, "bne $RA,$DISP",
-                 [(brcond (setne GPRC:$RA, 0), bb:$DISP)]>;
+                 [(brcond (setne GPRC:$RA, 0), bb:$DISP)], s_icbr>;
 
 //Branches, float
 def FBEQ : FBForm<0x31, "fbeq $RA,$DISP", 
-                  [(brcond (seteq F8RC:$RA, immFPZ), bb:$DISP)]>;
+                  [(brcond (seteq F8RC:$RA, immFPZ), bb:$DISP)], s_fbr>;
 def FBGE : FBForm<0x36, "fbge $RA,$DISP",
-                  [(brcond (setge F8RC:$RA, immFPZ), bb:$DISP)]>;
+                  [(brcond (setge F8RC:$RA, immFPZ), bb:$DISP)], s_fbr>;
 def FBGT : FBForm<0x37, "fbgt $RA,$DISP",
-                  [(brcond (setgt F8RC:$RA, immFPZ), bb:$DISP)]>;
+                  [(brcond (setgt F8RC:$RA, immFPZ), bb:$DISP)], s_fbr>;
 def FBLE : FBForm<0x33, "fble $RA,$DISP",
-                  [(brcond (setle F8RC:$RA, immFPZ), bb:$DISP)]>;
+                  [(brcond (setle F8RC:$RA, immFPZ), bb:$DISP)], s_fbr>;
 def FBLT : FBForm<0x32, "fblt $RA,$DISP",
-                  [(brcond (setlt F8RC:$RA, immFPZ), bb:$DISP)]>;
+                  [(brcond (setlt F8RC:$RA, immFPZ), bb:$DISP)], s_fbr>;
 def FBNE : FBForm<0x35, "fbne $RA,$DISP",
-                  [(brcond (setne F8RC:$RA, immFPZ), bb:$DISP)]>;
+                  [(brcond (setne F8RC:$RA, immFPZ), bb:$DISP)], s_fbr>;
 }
 
 def : Pat<(brcond GPRC:$RA, bb:$DISP), (BNE GPRC:$RA, bb:$DISP)>;
diff --git a/lib/Target/Alpha/AlphaSchedule.td b/lib/Target/Alpha/AlphaSchedule.td
new file mode 100644
index 0000000000..b3aab97aa4
--- /dev/null
+++ b/lib/Target/Alpha/AlphaSchedule.td
@@ -0,0 +1,84 @@
+//===- AlphaSchedule.td - Alpha Scheduling Definitions -----*- tablegen -*-===//
+// 
+//                     The LLVM Compiler Infrastructure
+//
+// This file was developed by Andrew Lenharth and is distributed under
+// the University of Illinois Open Source License. See LICENSE.TXT for details.
+// 
+//===----------------------------------------------------------------------===//
+
+//This is table 2-2 from the 21264 compiler writers guide
+//modified some
+
+//Pipelines
+
+def L0   : FuncUnit;
+def L1   : FuncUnit;
+def FST0 : FuncUnit;
+def FST1 : FuncUnit;
+def U0   : FuncUnit;
+def U1   : FuncUnit;
+def FA   : FuncUnit;
+def FM   : FuncUnit;
+
+def s_ild   : InstrItinClass;
+def s_fld   : InstrItinClass;
+def s_ist   : InstrItinClass;
+def s_fst   : InstrItinClass;
+def s_lda   : InstrItinClass;
+def s_rpcc  : InstrItinClass;
+def s_rx    : InstrItinClass;
+def s_mxpr  : InstrItinClass;
+def s_icbr  : InstrItinClass;
+def s_ubr   : InstrItinClass;
+def s_jsr   : InstrItinClass;
+def s_iadd  : InstrItinClass;
+def s_ilog  : InstrItinClass;
+def s_ishf  : InstrItinClass;
+def s_cmov  : InstrItinClass;
+def s_imul  : InstrItinClass;
+def s_imisc : InstrItinClass;
+def s_fbr   : InstrItinClass;
+def s_fadd  : InstrItinClass;
+def s_fmul  : InstrItinClass;
+def s_fcmov : InstrItinClass;
+def s_fdivt : InstrItinClass;
+def s_fdivs : InstrItinClass;
+def s_fsqrts: InstrItinClass;
+def s_fsqrtt: InstrItinClass;
+def s_ftoi  : InstrItinClass;
+def s_itof  : InstrItinClass;
+def s_pseudo : InstrItinClass;
+
+//Table 2­4 Instruction Class Latency in Cycles
+//modified some
+
+def Alpha21264Itineraries : ProcessorItineraries<[
+  InstrItinData<s_ild    , [InstrStage<3, [L0, L1]>]>,
+  InstrItinData<s_fld    , [InstrStage<4, [L0, L1]>]>,
+  InstrItinData<s_ist    , [InstrStage<0, [L0, L1]>]>,
+  InstrItinData<s_fst    , [InstrStage<0, [FST0, FST1, L0, L1]>]>,
+  InstrItinData<s_lda    , [InstrStage<1, [L0, L1, U0, U1]>]>,
+  InstrItinData<s_rpcc   , [InstrStage<1, [L1]>]>,
+  InstrItinData<s_rx     , [InstrStage<1, [L1]>]>,
+  InstrItinData<s_mxpr   , [InstrStage<1, [L0, L1]>]>,
+  InstrItinData<s_icbr   , [InstrStage<0, [U0, U1]>]>,
+  InstrItinData<s_ubr    , [InstrStage<3, [U0, U1]>]>,
+  InstrItinData<s_jsr    , [InstrStage<3, [L0]>]>,
+  InstrItinData<s_iadd   , [InstrStage<1, [L0, U0, L1, U1]>]>,
+  InstrItinData<s_ilog   , [InstrStage<1, [L0, U0, L1, U1]>]>,
+  InstrItinData<s_ishf   , [InstrStage<1, [U0, U1]>]>,
+  InstrItinData<s_cmov   , [InstrStage<1, [L0, U0, L1, U1]>]>,
+  InstrItinData<s_imul   , [InstrStage<7, [U1]>]>,
+  InstrItinData<s_imisc  , [InstrStage<3, [U0]>]>,
+  InstrItinData<s_fbr    , [InstrStage<0, [FA]>]>,
+  InstrItinData<s_fadd   , [InstrStage<6, [FA]>]>,
+  InstrItinData<s_fmul   , [InstrStage<6, [FM]>]>,
+  InstrItinData<s_fcmov  , [InstrStage<6, [FA]>]>,
+  InstrItinData<s_fdivs  , [InstrStage<12, [FA]>]>,
+  InstrItinData<s_fdivt  , [InstrStage<15, [FA]>]>,
+  InstrItinData<s_fsqrts , [InstrStage<18, [FA]>]>,
+  InstrItinData<s_fsqrtt , [InstrStage<33, [FA]>]>,
+  InstrItinData<s_ftoi   , [InstrStage<3, [FST0, FST1, L0, L1]>]>,
+  InstrItinData<s_itof   , [InstrStage<4, [L0, L1]>]>
+]>;
diff --git a/lib/Target/Alpha/AlphaSubtarget.h b/lib/Target/Alpha/AlphaSubtarget.h
index ea61ec7ef0..1b1ddc7c8b 100644
--- a/lib/Target/Alpha/AlphaSubtarget.h
+++ b/lib/Target/Alpha/AlphaSubtarget.h
@@ -14,6 +14,7 @@
 #ifndef ALPHASUBTARGET_H
 #define ALPHASUBTARGET_H
 
+#include "llvm/Target/TargetInstrItineraries.h"
 #include "llvm/Target/TargetSubtarget.h"
 
 #include <string>
@@ -28,6 +29,8 @@ protected:
   bool HasF2I;
   bool HasCT;
 
+  InstrItineraryData InstrItins;
+
 public:
   /// This constructor initializes the data members to match that
   /// of the specified module.