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| author | Jakob Stoklund Olesen <stoklund@2pi.dk> | 2009-08-02 21:49:05 +0000 |
|---|---|---|
| committer | Jakob Stoklund Olesen <stoklund@2pi.dk> | 2009-08-02 21:49:05 +0000 |
| commit | 1391cc19d0d0dec015bfc0130e4238cacd19fbf2 (patch) | |
| tree | 2ebeae1d9be6583afb05eef5c78fccd803af40e8 /lib/Target/Blackfin/BlackfinInstrInfo.td | |
| parent | a9a03f9c127c701da95339ebf3cecf9c7a027c0e (diff) | |
| download | llvm-1391cc19d0d0dec015bfc0130e4238cacd19fbf2.tar.gz llvm-1391cc19d0d0dec015bfc0130e4238cacd19fbf2.tar.bz2 llvm-1391cc19d0d0dec015bfc0130e4238cacd19fbf2.tar.xz | |
Remove unneeded intrinsics from Blackfin backend.
__builtin_bfin_ones does the same as ctpop, so it can be implemented in the front-end.
__builtin_bfin_loadbytes loads from an unaligned pointer with the disalignexcpt instruction. It does the same as loading from a pointer with the low bits masked. It is better if the front-end creates a masked load. We can always instruction select the masked to disalignexcpt+load.
We keep csync/ssync/idle. These intrinsics represent instructions that need workarounds for some silicon revisions. We may even want to convert inline assembler to intrinsics to enable the workarounds.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77917 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/Blackfin/BlackfinInstrInfo.td')
| -rw-r--r-- | lib/Target/Blackfin/BlackfinInstrInfo.td | 8 |
1 files changed, 1 insertions, 7 deletions
diff --git a/lib/Target/Blackfin/BlackfinInstrInfo.td b/lib/Target/Blackfin/BlackfinInstrInfo.td index 6faec27143..b0a2cc13c4 100644 --- a/lib/Target/Blackfin/BlackfinInstrInfo.td +++ b/lib/Target/Blackfin/BlackfinInstrInfo.td @@ -672,9 +672,8 @@ def NBITTST: F1<(outs JustCC:$cc), (ins D:$src1, uimm5mask:$src2), def ONES: F2<(outs D16L:$dst), (ins D:$src), "$dst = ones $src;", - [(set D16L:$dst, (int_bfin_ones D:$src))]>; + [(set D16L:$dst, (trunc (ctpop D:$src)))]>; -def : Pat<(i16 (trunc (ctpop D:$src))), (ONES D:$src)>; def : Pat<(ctpop D:$src), (MOVEzext (ONES D:$src))>; //===----------------------------------------------------------------------===// @@ -848,11 +847,6 @@ def ALIGN24 : F2<(outs D:$dst), (ins D:$src1, D:$src2), def DISALGNEXCPT : F2<(outs), (ins), "disalignexcpt;", []>; -// This is really two instructions in parallel, but we don't support vliw yet -def DISALGNEXCPT_LOAD : F2<(outs D:$dst), (ins I:$ptr), - "disalignexcpt \\|\\| $dst = [$ptr];", - [(set D:$dst, (int_bfin_loadbytes I:$ptr))]>; - // TODO: BYTEOP3P, BYTEOP16P, BYTEOP1P, BYTEOP2P, BYTEOP16M, SAA, // BYTEPACK, BYTEUNPACK |