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author | Eric Christopher <echristo@apple.com> | 2011-06-29 19:30:29 +0000 |
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committer | Eric Christopher <echristo@apple.com> | 2011-06-29 19:30:29 +0000 |
commit | 1c24ba9fad4e668ad854f1ff544e60c347c6d341 (patch) | |
tree | f55e1500229c3f917f88068ada56d3204c2ba1b5 /lib/Target/Blackfin | |
parent | 193f7e2eb01943900779e51513d6f5e709326dfa (diff) | |
download | llvm-1c24ba9fad4e668ad854f1ff544e60c347c6d341.tar.gz llvm-1c24ba9fad4e668ad854f1ff544e60c347c6d341.tar.bz2 llvm-1c24ba9fad4e668ad854f1ff544e60c347c6d341.tar.xz |
Move the Blackfin port away from getRegClassForInlineAsmConstraint by
creating a few specific register classes.
Part of rdar://9643582
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134086 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/Blackfin')
-rw-r--r-- | lib/Target/Blackfin/BlackfinISelLowering.cpp | 34 | ||||
-rw-r--r-- | lib/Target/Blackfin/BlackfinISelLowering.h | 3 | ||||
-rw-r--r-- | lib/Target/Blackfin/BlackfinRegisterInfo.td | 14 |
3 files changed, 22 insertions, 29 deletions
diff --git a/lib/Target/Blackfin/BlackfinISelLowering.cpp b/lib/Target/Blackfin/BlackfinISelLowering.cpp index 588d9bded8..d5728324de 100644 --- a/lib/Target/Blackfin/BlackfinISelLowering.cpp +++ b/lib/Target/Blackfin/BlackfinISelLowering.cpp @@ -621,39 +621,21 @@ getRegForInlineAsmConstraint(const std::string &Constraint, EVT VT) const { case 'w': return Pair(0U, ALLRegisterClass); case 'Z': return Pair(P3, PRegisterClass); case 'Y': return Pair(P1, PRegisterClass); + case 'z': return Pair(0U, zConsRegisterClass); + case 'D': return Pair(0U, DConsRegisterClass); + case 'W': return Pair(0U, WConsRegisterClass); + case 'c': return Pair(0U, cConsRegisterClass); + case 't': return Pair(0U, tConsRegisterClass); + case 'u': return Pair(0U, uConsRegisterClass); + case 'k': return Pair(0U, kConsRegisterClass); + case 'y': return Pair(0U, yConsRegisterClass); } // Not implemented: q0-q7, qA. Use {R2} etc instead. - // Constraints z, D, W, c, t, u, k, and y use non-existing classes, defer to - // getRegClassForInlineAsmConstraint() return TargetLowering::getRegForInlineAsmConstraint(Constraint, VT); } -std::vector<unsigned> BlackfinTargetLowering:: -getRegClassForInlineAsmConstraint(const std::string &Constraint, EVT VT) const { - using namespace BF; - - if (Constraint.size() != 1) - return std::vector<unsigned>(); - - switch (Constraint[0]) { - case 'z': return make_vector<unsigned>(P0, P1, P2, 0); - case 'D': return make_vector<unsigned>(R0, R2, R4, R6, 0); - case 'W': return make_vector<unsigned>(R1, R3, R5, R7, 0); - case 'c': return make_vector<unsigned>(I0, I1, I2, I3, - B0, B1, B2, B3, - L0, L1, L2, L3, 0); - case 't': return make_vector<unsigned>(LT0, LT1, 0); - case 'u': return make_vector<unsigned>(LB0, LB1, 0); - case 'k': return make_vector<unsigned>(LC0, LC1, 0); - case 'y': return make_vector<unsigned>(RETS, RETN, RETI, RETX, RETE, - ASTAT, SEQSTAT, USP, 0); - } - - return std::vector<unsigned>(); -} - bool BlackfinTargetLowering:: isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const { // The Blackfin target isn't yet aware of offsets. diff --git a/lib/Target/Blackfin/BlackfinISelLowering.h b/lib/Target/Blackfin/BlackfinISelLowering.h index 9a54557ad5..b65775b928 100644 --- a/lib/Target/Blackfin/BlackfinISelLowering.h +++ b/lib/Target/Blackfin/BlackfinISelLowering.h @@ -48,9 +48,6 @@ namespace llvm { std::pair<unsigned, const TargetRegisterClass*> getRegForInlineAsmConstraint(const std::string &Constraint, EVT VT) const; - std::vector<unsigned> - getRegClassForInlineAsmConstraint(const std::string &Constraint, - EVT VT) const; virtual bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const; const char *getTargetNodeName(unsigned Opcode) const; diff --git a/lib/Target/Blackfin/BlackfinRegisterInfo.td b/lib/Target/Blackfin/BlackfinRegisterInfo.td index 0d502fdcc7..1c42205eb7 100644 --- a/lib/Target/Blackfin/BlackfinRegisterInfo.td +++ b/lib/Target/Blackfin/BlackfinRegisterInfo.td @@ -261,3 +261,17 @@ def StatBit : RegisterClass<"BF", [i1], 8, // Should be i40, but that isn't defined. It is not a legal type yet anyway. def Accu : RegisterClass<"BF", [i64], 64, (add A0, A1)>; + +// Register classes to match inline asm constraints. +def zCons : RegisterClass<"BF", [i32], 32, (add P0, P1, P2)>; +def DCons : RegisterClass<"BF", [i32], 32, (add R0, R2, R4, R6)>; +def WCons : RegisterClass<"BF", [i32], 32, (add R1, R3, R5, R7)>; +def cCons : RegisterClass<"BF", [i32], 32, (add I0, I1, I2, I3, + B0, B1, B2, B3, + L0, L1, L2, L3)>; +def tCons : RegisterClass<"BF", [i32], 32, (add LT0, LT1)>; +def uCons : RegisterClass<"BF", [i32], 32, (add LB0, LB1)>; +def kCons : RegisterClass<"BF", [i32], 32, (add LC0, LC1)>; +def yCons : RegisterClass<"BF", [i32], 32, (add RETS, RETN, RETI, RETX, + RETE, ASTAT, SEQSTAT, + USP)>; |