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| author | Duncan Sands <baldrick@free.fr> | 2011-09-06 19:07:46 +0000 |
|---|---|---|
| committer | Duncan Sands <baldrick@free.fr> | 2011-09-06 19:07:46 +0000 |
| commit | 28b77e968d2b01fc9da724762bd8ddcd80650e32 (patch) | |
| tree | 711ee16dd99789ee82f4891e436cdd38535667da /lib/Target/Blackfin | |
| parent | 4a51708448e8958d8d1a375c055f1b98c8e20926 (diff) | |
| download | llvm-28b77e968d2b01fc9da724762bd8ddcd80650e32.tar.gz llvm-28b77e968d2b01fc9da724762bd8ddcd80650e32.tar.bz2 llvm-28b77e968d2b01fc9da724762bd8ddcd80650e32.tar.xz | |
Add codegen support for vector select (in the IR this means a select
with a vector condition); such selects become VSELECT codegen nodes.
This patch also removes VSETCC codegen nodes, unifying them with SETCC
nodes (codegen was actually often using SETCC for vector SETCC already).
This ensures that various DAG combiner optimizations kick in for vector
comparisons. Passes dragonegg bootstrap with no testsuite regressions
(nightly testsuite as well as "make check-all"). Patch mostly by
Nadav Rotem.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139159 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/Blackfin')
| -rw-r--r-- | lib/Target/Blackfin/BlackfinISelLowering.cpp | 3 | ||||
| -rw-r--r-- | lib/Target/Blackfin/BlackfinISelLowering.h | 2 |
2 files changed, 3 insertions, 2 deletions
diff --git a/lib/Target/Blackfin/BlackfinISelLowering.cpp b/lib/Target/Blackfin/BlackfinISelLowering.cpp index 43aad43340..7d4c45fdf6 100644 --- a/lib/Target/Blackfin/BlackfinISelLowering.cpp +++ b/lib/Target/Blackfin/BlackfinISelLowering.cpp @@ -42,6 +42,7 @@ using namespace llvm; BlackfinTargetLowering::BlackfinTargetLowering(TargetMachine &TM) : TargetLowering(TM, new TargetLoweringObjectFileELF()) { setBooleanContents(ZeroOrOneBooleanContent); + setBooleanVectorContents(ZeroOrOneBooleanContent); // FIXME: Is this correct? setStackPointerRegisterToSaveRestore(BF::SP); setIntDivIsCheap(false); @@ -135,7 +136,7 @@ const char *BlackfinTargetLowering::getTargetNodeName(unsigned Opcode) const { } } -MVT::SimpleValueType BlackfinTargetLowering::getSetCCResultType(EVT VT) const { +EVT BlackfinTargetLowering::getSetCCResultType(EVT VT) const { // SETCC always sets the CC register. Technically that is an i1 register, but // that type is not legal, so we treat it as an i32 register. return MVT::i32; diff --git a/lib/Target/Blackfin/BlackfinISelLowering.h b/lib/Target/Blackfin/BlackfinISelLowering.h index b65775b928..90908baaae 100644 --- a/lib/Target/Blackfin/BlackfinISelLowering.h +++ b/lib/Target/Blackfin/BlackfinISelLowering.h @@ -33,7 +33,7 @@ namespace llvm { public: BlackfinTargetLowering(TargetMachine &TM); virtual MVT getShiftAmountTy(EVT LHSTy) const { return MVT::i16; } - virtual MVT::SimpleValueType getSetCCResultType(EVT VT) const; + virtual EVT getSetCCResultType(EVT VT) const; virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const; virtual void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue> &Results, |