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author | Evan Cheng <evan.cheng@apple.com> | 2011-06-24 01:44:41 +0000 |
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committer | Evan Cheng <evan.cheng@apple.com> | 2011-06-24 01:44:41 +0000 |
commit | a347f85dbeee37a7f2bb68df1a7d4cdfbb7b576d (patch) | |
tree | 843b1f6be5ffffef461ce063cf5468368598d40e /lib/Target/Blackfin | |
parent | 66dddd1da3e036d05f94df82221a97b7d26e3498 (diff) | |
download | llvm-a347f85dbeee37a7f2bb68df1a7d4cdfbb7b576d.tar.gz llvm-a347f85dbeee37a7f2bb68df1a7d4cdfbb7b576d.tar.bz2 llvm-a347f85dbeee37a7f2bb68df1a7d4cdfbb7b576d.tar.xz |
Starting to refactor Target to separate out code that's needed to fully describe
target machine from those that are only needed by codegen. The goal is to
sink the essential target description into MC layer so we can start building
MC based tools without needing to link in the entire codegen.
First step is to refactor TargetRegisterInfo. This patch added a base class
MCRegisterInfo which TargetRegisterInfo is derived from. Changed TableGen to
separate register description from the rest of the stuff.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133782 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/Blackfin')
-rw-r--r-- | lib/Target/Blackfin/BlackfinRegisterInfo.cpp | 8 | ||||
-rw-r--r-- | lib/Target/Blackfin/CMakeLists.txt | 5 | ||||
-rw-r--r-- | lib/Target/Blackfin/Makefile | 5 |
3 files changed, 10 insertions, 8 deletions
diff --git a/lib/Target/Blackfin/BlackfinRegisterInfo.cpp b/lib/Target/Blackfin/BlackfinRegisterInfo.cpp index 6ca460ef80..6377d8e403 100644 --- a/lib/Target/Blackfin/BlackfinRegisterInfo.cpp +++ b/lib/Target/Blackfin/BlackfinRegisterInfo.cpp @@ -29,11 +29,14 @@ #include "llvm/Type.h" #include "llvm/ADT/BitVector.h" #include "llvm/ADT/STLExtras.h" +#include "BlackfinGenRegisterDesc.inc" +#include "BlackfinGenRegisterInfo.inc" using namespace llvm; BlackfinRegisterInfo::BlackfinRegisterInfo(BlackfinSubtarget &st, const TargetInstrInfo &tii) - : BlackfinGenRegisterInfo(BF::ADJCALLSTACKDOWN, BF::ADJCALLSTACKUP), + : BlackfinGenRegisterInfo(BlackfinRegDesc, BlackfinRegInfoDesc, + BF::ADJCALLSTACKDOWN, BF::ADJCALLSTACKUP), Subtarget(st), TII(tii) {} @@ -356,6 +359,3 @@ int BlackfinRegisterInfo::getLLVMRegNum(unsigned DwarfRegNum, llvm_unreachable("What is the dwarf register number"); return -1; } - -#include "BlackfinGenRegisterInfo.inc" - diff --git a/lib/Target/Blackfin/CMakeLists.txt b/lib/Target/Blackfin/CMakeLists.txt index a47299ff16..10896c5864 100644 --- a/lib/Target/Blackfin/CMakeLists.txt +++ b/lib/Target/Blackfin/CMakeLists.txt @@ -1,8 +1,9 @@ set(LLVM_TARGET_DEFINITIONS Blackfin.td) -tablegen(BlackfinGenRegisterInfo.h.inc -gen-register-desc-header) tablegen(BlackfinGenRegisterNames.inc -gen-register-enums) -tablegen(BlackfinGenRegisterInfo.inc -gen-register-desc) +tablegen(BlackfinGenRegisterDesc.inc -gen-register-desc) +tablegen(BlackfinGenRegisterInfo.h.inc -gen-register-info-header) +tablegen(BlackfinGenRegisterInfo.inc -gen-register-info) tablegen(BlackfinGenInstrNames.inc -gen-instr-enums) tablegen(BlackfinGenInstrInfo.inc -gen-instr-desc) tablegen(BlackfinGenAsmWriter.inc -gen-asm-writer) diff --git a/lib/Target/Blackfin/Makefile b/lib/Target/Blackfin/Makefile index 5eb8e9a992..8ea1dfb067 100644 --- a/lib/Target/Blackfin/Makefile +++ b/lib/Target/Blackfin/Makefile @@ -12,8 +12,9 @@ LIBRARYNAME = LLVMBlackfinCodeGen TARGET = Blackfin # Make sure that tblgen is run, first thing. -BUILT_SOURCES = BlackfinGenRegisterInfo.h.inc BlackfinGenRegisterNames.inc \ - BlackfinGenRegisterInfo.inc BlackfinGenInstrNames.inc \ +BUILT_SOURCES = BlackfinGenRegisterNames.inc BlackfinGenRegisterDesc.inc \ + BlackfinGenRegisterInfo.h.inc BlackfinGenRegisterInfo.inc \ + BlackfinGenInstrNames.inc \ BlackfinGenInstrInfo.inc BlackfinGenAsmWriter.inc \ BlackfinGenDAGISel.inc BlackfinGenSubtarget.inc \ BlackfinGenCallingConv.inc BlackfinGenIntrinsics.inc |