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author | Jakob Stoklund Olesen <stoklund@2pi.dk> | 2010-05-26 01:21:14 +0000 |
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committer | Jakob Stoklund Olesen <stoklund@2pi.dk> | 2010-05-26 01:21:14 +0000 |
commit | b555609e73f5091bf8180c0875fb1fa6c5ad0e7a (patch) | |
tree | 96d997b82dbd5e9fa80e40dd406b0e55db187b2d /lib/Target/Blackfin | |
parent | a4e4ffd389497eb28f5fe91521fb71da4340e5d6 (diff) | |
download | llvm-b555609e73f5091bf8180c0875fb1fa6c5ad0e7a.tar.gz llvm-b555609e73f5091bf8180c0875fb1fa6c5ad0e7a.tar.bz2 llvm-b555609e73f5091bf8180c0875fb1fa6c5ad0e7a.tar.xz |
Revert "Replace the SubRegSet tablegen class with a less error-prone mechanism."
This reverts commit 104654.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104660 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/Blackfin')
-rw-r--r-- | lib/Target/Blackfin/BlackfinRegisterInfo.td | 28 |
1 files changed, 24 insertions, 4 deletions
diff --git a/lib/Target/Blackfin/BlackfinRegisterInfo.td b/lib/Target/Blackfin/BlackfinRegisterInfo.td index e1cfae9044..8379ce74a2 100644 --- a/lib/Target/Blackfin/BlackfinRegisterInfo.td +++ b/lib/Target/Blackfin/BlackfinRegisterInfo.td @@ -19,7 +19,6 @@ let Namespace = "BF" in { def lo16 : SubRegIndex; def hi16 : SubRegIndex; def lo32 : SubRegIndex; -def hi32 : SubRegIndex; } // Registers are identified with 3-bit group and 3-bit ID numbers. @@ -50,7 +49,6 @@ class Ri<bits<3> group, bits<3> num, string n> : BlackfinReg<n> { // Ra 40-bit accumulator registers class Ra<bits<3> num, string n, list<Register> subs> : BlackfinReg<n> { let SubRegs = subs; - let SubRegIndices = [hi32, lo32]; let Group = 4; let Num = num; } @@ -65,7 +63,6 @@ multiclass Rss<bits<3> group, bits<3> num, string n> { class Rii<bits<3> group, bits<3> num, string n, list<Register> subs> : BlackfinReg<n> { let SubRegs = subs; - let SubRegIndices = [hi16, lo16]; let Group = group; let Num = num; } @@ -176,7 +173,7 @@ def RETN : Ri<7, 5, "retn">, DwarfRegNum<[38]>; def RETE : Ri<7, 6, "rete">, DwarfRegNum<[39]>; def ASTAT : Ri<4, 6, "astat">, DwarfRegNum<[40]> { - let Aliases = [AZ, AN, CC, NCC, AQ, AC0, AC1, AV0, AV0S, AV1, AV1S, V, VS]; + let SubRegs = [AZ, AN, CC, NCC, AQ, AC0, AC1, AV0, AV0S, AV1, AV1S, V, VS]; } def SEQSTAT : Ri<7, 1, "seqstat">, DwarfRegNum<[41]>; @@ -194,6 +191,29 @@ def LC1 : Ri<6, 3, "lc1">, DwarfRegNum<[47]>; def LB0 : Ri<6, 2, "lb0">, DwarfRegNum<[48]>; def LB1 : Ri<6, 5, "lb1">, DwarfRegNum<[49]>; +def : SubRegSet<lo16, + [R0, R1, R2, R3, R4, R5, R6, R7, + P0, P1, P2, P3, P4, P5, SP, FP, + I0, I1, I2, I3, M0, M1, M2, M3, + B0, B1, B2, B3, L0, L1, L2, L3], + [R0L, R1L, R2L, R3L, R4L, R5L, R6L, R7L, + P0L, P1L, P2L, P3L, P4L, P5L, SPL, FPL, + I0L, I1L, I2L, I3L, M0L, M1L, M2L, M3L, + B0L, B1L, B2L, B3L, L0L, L1L, L2L, L3L]>; + +def : SubRegSet<hi16, + [R0, R1, R2, R3, R4, R5, R6, R7, + P0, P1, P2, P3, P4, P5, SP, FP, + I0, I1, I2, I3, M0, M1, M2, M3, + B0, B1, B2, B3, L0, L1, L2, L3], + [R0H, R1H, R2H, R3H, R4H, R5H, R6H, R7H, + P0H, P1H, P2H, P3H, P4H, P5H, SPH, FPH, + I0H, I1H, I2H, I3H, M0H, M1H, M2H, M3H, + B0H, B1H, B2H, B3H, L0H, L1H, L2H, L3H]>; + +def : SubRegSet<lo16, [A0, A0W, A1, A1W], [A0L, A0L, A1L, A1L]>; +def : SubRegSet<hi16, [A0, A0W, A1, A1W], [A0H, A0H, A1H, A1H]>; + // Register classes. def D16 : RegisterClass<"BF", [i16], 16, [R0H, R0L, R1H, R1L, R2H, R2L, R3H, R3L, |