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authorScott Michel <scottm@aero.org>2007-12-20 00:44:13 +0000
committerScott Michel <scottm@aero.org>2007-12-20 00:44:13 +0000
commit86c041f50e17f7fcd18193ff49e58379924d6472 (patch)
tree581d062c9cd0bb0df1a7a8ab5f6d65ca66fdb572 /lib/Target/CellSPU/SPURegisterInfo.cpp
parente3611871cb5430f9c958cab1be7ef2e0778b3241 (diff)
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More working CellSPU tests:
- vec_const.ll: Vector constant loads - immed64.ll: i64, f64 constant loads git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45242 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/CellSPU/SPURegisterInfo.cpp')
-rw-r--r--lib/Target/CellSPU/SPURegisterInfo.cpp6
1 files changed, 4 insertions, 2 deletions
diff --git a/lib/Target/CellSPU/SPURegisterInfo.cpp b/lib/Target/CellSPU/SPURegisterInfo.cpp
index 26917fe21c..7ef134cd12 100644
--- a/lib/Target/CellSPU/SPURegisterInfo.cpp
+++ b/lib/Target/CellSPU/SPURegisterInfo.cpp
@@ -378,11 +378,13 @@ void SPURegisterInfo::copyRegToReg(MachineBasicBlock &MBB,
} else if (DestRC == SPU::R32CRegisterClass) {
BuildMI(MBB, MI, TII.get(SPU::ORIr32), DestReg).addReg(SrcReg).addImm(0);
} else if (DestRC == SPU::R32FPRegisterClass) {
- BuildMI(MBB, MI, TII.get(SPU::ORIf32), DestReg).addReg(SrcReg).addImm(0);
+ BuildMI(MBB, MI, TII.get(SPU::ORf32), DestReg).addReg(SrcReg)
+ .addReg(SrcReg);
} else if (DestRC == SPU::R64CRegisterClass) {
BuildMI(MBB, MI, TII.get(SPU::ORIr64), DestReg).addReg(SrcReg).addImm(0);
} else if (DestRC == SPU::R64FPRegisterClass) {
- BuildMI(MBB, MI, TII.get(SPU::ORIf64), DestReg).addReg(SrcReg).addImm(0);
+ BuildMI(MBB, MI, TII.get(SPU::ORf64), DestReg).addReg(SrcReg)
+ .addReg(SrcReg);
} else if (DestRC == SPU::GPRCRegisterClass) {
BuildMI(MBB, MI, TII.get(SPU::ORgprc), DestReg).addReg(SrcReg)
.addReg(SrcReg);