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author | Owen Anderson <resistor@mac.com> | 2008-01-01 21:11:32 +0000 |
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committer | Owen Anderson <resistor@mac.com> | 2008-01-01 21:11:32 +0000 |
commit | f6372aa1cc568df19da7c5023e83c75aa9404a07 (patch) | |
tree | 9cc85598bdfe4e6af602fffcca57f03c61c0dc3f /lib/Target/CellSPU/SPURegisterInfo.cpp | |
parent | 80fe5311b5e9e5c4642ff46ba2377173c17797f6 (diff) | |
download | llvm-f6372aa1cc568df19da7c5023e83c75aa9404a07.tar.gz llvm-f6372aa1cc568df19da7c5023e83c75aa9404a07.tar.bz2 llvm-f6372aa1cc568df19da7c5023e83c75aa9404a07.tar.xz |
Move some more instruction creation methods from RegisterInfo into InstrInfo.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45484 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/CellSPU/SPURegisterInfo.cpp')
-rw-r--r-- | lib/Target/CellSPU/SPURegisterInfo.cpp | 169 |
1 files changed, 0 insertions, 169 deletions
diff --git a/lib/Target/CellSPU/SPURegisterInfo.cpp b/lib/Target/CellSPU/SPURegisterInfo.cpp index a05ab41902..3a0565d955 100644 --- a/lib/Target/CellSPU/SPURegisterInfo.cpp +++ b/lib/Target/CellSPU/SPURegisterInfo.cpp @@ -191,175 +191,6 @@ SPURegisterInfo::SPURegisterInfo(const SPUSubtarget &subtarget, { } -void -SPURegisterInfo::storeRegToStackSlot(MachineBasicBlock &MBB, - MachineBasicBlock::iterator MI, - unsigned SrcReg, bool isKill, int FrameIdx, - const TargetRegisterClass *RC) const -{ - MachineOpCode opc; - if (RC == SPU::GPRCRegisterClass) { - opc = (FrameIdx < SPUFrameInfo::maxFrameOffset()) - ? SPU::STQDr128 - : SPU::STQXr128; - } else if (RC == SPU::R64CRegisterClass) { - opc = (FrameIdx < SPUFrameInfo::maxFrameOffset()) - ? SPU::STQDr64 - : SPU::STQXr64; - } else if (RC == SPU::R64FPRegisterClass) { - opc = (FrameIdx < SPUFrameInfo::maxFrameOffset()) - ? SPU::STQDr64 - : SPU::STQXr64; - } else if (RC == SPU::R32CRegisterClass) { - opc = (FrameIdx < SPUFrameInfo::maxFrameOffset()) - ? SPU::STQDr32 - : SPU::STQXr32; - } else if (RC == SPU::R32FPRegisterClass) { - opc = (FrameIdx < SPUFrameInfo::maxFrameOffset()) - ? SPU::STQDr32 - : SPU::STQXr32; - } else if (RC == SPU::R16CRegisterClass) { - opc = (FrameIdx < SPUFrameInfo::maxFrameOffset()) ? - SPU::STQDr16 - : SPU::STQXr16; - } else { - assert(0 && "Unknown regclass!"); - abort(); - } - - addFrameReference(BuildMI(MBB, MI, TII.get(opc)) - .addReg(SrcReg, false, false, isKill), FrameIdx); -} - -void SPURegisterInfo::storeRegToAddr(MachineFunction &MF, unsigned SrcReg, - bool isKill, - SmallVectorImpl<MachineOperand> &Addr, - const TargetRegisterClass *RC, - SmallVectorImpl<MachineInstr*> &NewMIs) const { - cerr << "storeRegToAddr() invoked!\n"; - abort(); - - if (Addr[0].isFrameIndex()) { - /* do what storeRegToStackSlot does here */ - } else { - unsigned Opc = 0; - if (RC == SPU::GPRCRegisterClass) { - /* Opc = PPC::STW; */ - } else if (RC == SPU::R16CRegisterClass) { - /* Opc = PPC::STD; */ - } else if (RC == SPU::R32CRegisterClass) { - /* Opc = PPC::STFD; */ - } else if (RC == SPU::R32FPRegisterClass) { - /* Opc = PPC::STFD; */ - } else if (RC == SPU::R64FPRegisterClass) { - /* Opc = PPC::STFS; */ - } else if (RC == SPU::VECREGRegisterClass) { - /* Opc = PPC::STVX; */ - } else { - assert(0 && "Unknown regclass!"); - abort(); - } - MachineInstrBuilder MIB = BuildMI(TII.get(Opc)) - .addReg(SrcReg, false, false, isKill); - for (unsigned i = 0, e = Addr.size(); i != e; ++i) { - MachineOperand &MO = Addr[i]; - if (MO.isRegister()) - MIB.addReg(MO.getReg()); - else if (MO.isImmediate()) - MIB.addImm(MO.getImm()); - else - MIB.addFrameIndex(MO.getIndex()); - } - NewMIs.push_back(MIB); - } -} - -void -SPURegisterInfo::loadRegFromStackSlot(MachineBasicBlock &MBB, - MachineBasicBlock::iterator MI, - unsigned DestReg, int FrameIdx, - const TargetRegisterClass *RC) const -{ - MachineOpCode opc; - if (RC == SPU::GPRCRegisterClass) { - opc = (FrameIdx < SPUFrameInfo::maxFrameOffset()) - ? SPU::LQDr128 - : SPU::LQXr128; - } else if (RC == SPU::R64CRegisterClass) { - opc = (FrameIdx < SPUFrameInfo::maxFrameOffset()) - ? SPU::LQDr64 - : SPU::LQXr64; - } else if (RC == SPU::R64FPRegisterClass) { - opc = (FrameIdx < SPUFrameInfo::maxFrameOffset()) - ? SPU::LQDr64 - : SPU::LQXr64; - } else if (RC == SPU::R32CRegisterClass) { - opc = (FrameIdx < SPUFrameInfo::maxFrameOffset()) - ? SPU::LQDr32 - : SPU::LQXr32; - } else if (RC == SPU::R32FPRegisterClass) { - opc = (FrameIdx < SPUFrameInfo::maxFrameOffset()) - ? SPU::LQDr32 - : SPU::LQXr32; - } else if (RC == SPU::R16CRegisterClass) { - opc = (FrameIdx < SPUFrameInfo::maxFrameOffset()) - ? SPU::LQDr16 - : SPU::LQXr16; - } else { - assert(0 && "Unknown regclass in loadRegFromStackSlot!"); - abort(); - } - - addFrameReference(BuildMI(MBB, MI, TII.get(opc)).addReg(DestReg), FrameIdx); -} - -/*! - \note We are really pessimistic here about what kind of a load we're doing. - */ -void SPURegisterInfo::loadRegFromAddr(MachineFunction &MF, unsigned DestReg, - SmallVectorImpl<MachineOperand> &Addr, - const TargetRegisterClass *RC, - SmallVectorImpl<MachineInstr*> &NewMIs) - const { - cerr << "loadRegToAddr() invoked!\n"; - abort(); - - if (Addr[0].isFrameIndex()) { - /* do what loadRegFromStackSlot does here... */ - } else { - unsigned Opc = 0; - if (RC == SPU::R8CRegisterClass) { - /* do brilliance here */ - } else if (RC == SPU::R16CRegisterClass) { - /* Opc = PPC::LWZ; */ - } else if (RC == SPU::R32CRegisterClass) { - /* Opc = PPC::LD; */ - } else if (RC == SPU::R32FPRegisterClass) { - /* Opc = PPC::LFD; */ - } else if (RC == SPU::R64FPRegisterClass) { - /* Opc = PPC::LFS; */ - } else if (RC == SPU::VECREGRegisterClass) { - /* Opc = PPC::LVX; */ - } else if (RC == SPU::GPRCRegisterClass) { - /* Opc = something else! */ - } else { - assert(0 && "Unknown regclass!"); - abort(); - } - MachineInstrBuilder MIB = BuildMI(TII.get(Opc), DestReg); - for (unsigned i = 0, e = Addr.size(); i != e; ++i) { - MachineOperand &MO = Addr[i]; - if (MO.isRegister()) - MIB.addReg(MO.getReg()); - else if (MO.isImmediate()) - MIB.addImm(MO.getImm()); - else - MIB.addFrameIndex(MO.getIndex()); - } - NewMIs.push_back(MIB); - } -} - void SPURegisterInfo::reMaterialize(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, unsigned DestReg, |