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author | Evan Cheng <evan.cheng@apple.com> | 2011-07-11 03:57:24 +0000 |
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committer | Evan Cheng <evan.cheng@apple.com> | 2011-07-11 03:57:24 +0000 |
commit | 59ee62d2418df8db499eca1ae17f5900dc2dcbba (patch) | |
tree | 087be0d28a100c6e3fe071c6511469636439d20f /lib/Target/CellSPU | |
parent | b5a12dd12fa3cd1026e9058a53089c29fb97f2fd (diff) | |
download | llvm-59ee62d2418df8db499eca1ae17f5900dc2dcbba.tar.gz llvm-59ee62d2418df8db499eca1ae17f5900dc2dcbba.tar.bz2 llvm-59ee62d2418df8db499eca1ae17f5900dc2dcbba.tar.xz |
- Eliminate MCCodeEmitter's dependency on TargetMachine. It now uses MCInstrInfo
and MCSubtargetInfo.
- Added methods to update subtarget features (used when targets automatically
detect subtarget features or switch modes).
- Teach X86Subtarget to update MCSubtargetInfo features bits since the
MCSubtargetInfo layer can be shared with other modules.
- These fixes .code 16 / .code 32 support since mode switch is updated in
MCSubtargetInfo so MC code emitter can do the right thing.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134884 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/CellSPU')
-rw-r--r-- | lib/Target/CellSPU/SPUInstrInfo.cpp | 13 | ||||
-rw-r--r-- | lib/Target/CellSPU/SPUSubtarget.cpp | 2 |
2 files changed, 13 insertions, 2 deletions
diff --git a/lib/Target/CellSPU/SPUInstrInfo.cpp b/lib/Target/CellSPU/SPUInstrInfo.cpp index 93b6d4c556..12fae9df87 100644 --- a/lib/Target/CellSPU/SPUInstrInfo.cpp +++ b/lib/Target/CellSPU/SPUInstrInfo.cpp @@ -17,10 +17,11 @@ #include "SPUTargetMachine.h" #include "SPUHazardRecognizers.h" #include "llvm/CodeGen/MachineInstrBuilder.h" +#include "llvm/MC/MCContext.h" +#include "llvm/Target/TargetRegistry.h" #include "llvm/Support/Debug.h" #include "llvm/Support/ErrorHandling.h" #include "llvm/Support/raw_ostream.h" -#include "llvm/MC/MCContext.h" #define GET_INSTRINFO_CTOR #define GET_INSTRINFO_MC_DESC @@ -450,3 +451,13 @@ SPUInstrInfo::ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) return true; } + +MCInstrInfo *createSPUMCInstrInfo() { + MCInstrInfo *X = new MCInstrInfo(); + InitSPUMCInstrInfo(X); + return X; +} + +extern "C" void LLVMInitializeCellSPUMCInstrInfo() { + TargetRegistry::RegisterMCInstrInfo(TheCellSPUTarget, createSPUMCInstrInfo); +} diff --git a/lib/Target/CellSPU/SPUSubtarget.cpp b/lib/Target/CellSPU/SPUSubtarget.cpp index 3ce96b81a9..51fa1ea1b5 100644 --- a/lib/Target/CellSPU/SPUSubtarget.cpp +++ b/lib/Target/CellSPU/SPUSubtarget.cpp @@ -70,7 +70,7 @@ bool SPUSubtarget::enablePostRAScheduler( MCSubtargetInfo *createSPUMCSubtargetInfo(StringRef TT, StringRef CPU, StringRef FS) { MCSubtargetInfo *X = new MCSubtargetInfo(); - InitSPUMCSubtargetInfo(X, CPU, FS); + InitSPUMCSubtargetInfo(X, TT, CPU, FS); return X; } |