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| author | Chris Lattner <sabre@nondot.org> | 2011-04-15 05:18:47 +0000 |
|---|---|---|
| committer | Chris Lattner <sabre@nondot.org> | 2011-04-15 05:18:47 +0000 |
| commit | 7a2bdde0a0eebcd2125055e0eacaca040f0b766c (patch) | |
| tree | 1cd5fa470f290368855c9081cb213ed118812805 /lib/Target/CellSPU | |
| parent | bcb8c6d09ee426e0f774e3412912f6ae9e5f78dd (diff) | |
| download | llvm-7a2bdde0a0eebcd2125055e0eacaca040f0b766c.tar.gz llvm-7a2bdde0a0eebcd2125055e0eacaca040f0b766c.tar.bz2 llvm-7a2bdde0a0eebcd2125055e0eacaca040f0b766c.tar.xz | |
Fix a ton of comment typos found by codespell. Patch by
Luis Felipe Strano Moraes!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129558 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/CellSPU')
| -rw-r--r-- | lib/Target/CellSPU/SPU64InstrInfo.td | 2 | ||||
| -rw-r--r-- | lib/Target/CellSPU/SPUISelLowering.cpp | 2 |
2 files changed, 2 insertions, 2 deletions
diff --git a/lib/Target/CellSPU/SPU64InstrInfo.td b/lib/Target/CellSPU/SPU64InstrInfo.td index 5ef5716bd8..f340edfb0f 100644 --- a/lib/Target/CellSPU/SPU64InstrInfo.td +++ b/lib/Target/CellSPU/SPU64InstrInfo.td @@ -24,7 +24,7 @@ // 5. The code sequences for r64 and v2i64 are probably overly conservative, // compared to the code that gcc produces. // -// M00$E B!tes Kan be Pretty N@sTi!!!!! (appologies to Monty!) +// M00$E B!tes Kan be Pretty N@sTi!!!!! (apologies to Monty!) //-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~ // selb instruction definition for i64. Note that the selection mask is diff --git a/lib/Target/CellSPU/SPUISelLowering.cpp b/lib/Target/CellSPU/SPUISelLowering.cpp index 743a4d7a0f..8668da3ca2 100644 --- a/lib/Target/CellSPU/SPUISelLowering.cpp +++ b/lib/Target/CellSPU/SPUISelLowering.cpp @@ -705,7 +705,7 @@ LowerLOAD(SDValue Op, SelectionDAG &DAG, const SPUSubtarget *ST) { offset )); - // Shift the low similarily + // Shift the low similarly // TODO: add SPUISD::SHL_BYTES low = DAG.getNode(SPUISD::SHL_BYTES, dl, MVT::i128, low, offset ); |