summaryrefslogtreecommitdiff
path: root/lib/Target/Hexagon/HexagonCallingConvLower.h
diff options
context:
space:
mode:
authorBill Wendling <isanbard@gmail.com>2013-06-07 06:19:56 +0000
committerBill Wendling <isanbard@gmail.com>2013-06-07 06:19:56 +0000
commit54a56fad36a32f12709da5f96998336f08524be9 (patch)
treeb8ff9ae26a5ebd885ba1a05b8b9934b04bca9e6e /lib/Target/Hexagon/HexagonCallingConvLower.h
parent9eb856bc295eabe1ebff0325158e65050deddd56 (diff)
downloadllvm-54a56fad36a32f12709da5f96998336f08524be9.tar.gz
llvm-54a56fad36a32f12709da5f96998336f08524be9.tar.bz2
llvm-54a56fad36a32f12709da5f96998336f08524be9.tar.xz
Don't cache the instruction and register info from the TargetMachine, because
the internals of TargetMachine could change. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183490 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/Hexagon/HexagonCallingConvLower.h')
-rw-r--r--lib/Target/Hexagon/HexagonCallingConvLower.h1
1 files changed, 0 insertions, 1 deletions
diff --git a/lib/Target/Hexagon/HexagonCallingConvLower.h b/lib/Target/Hexagon/HexagonCallingConvLower.h
index 489b3a3e59..eed99f42c2 100644
--- a/lib/Target/Hexagon/HexagonCallingConvLower.h
+++ b/lib/Target/Hexagon/HexagonCallingConvLower.h
@@ -48,7 +48,6 @@ class Hexagon_CCState {
CallingConv::ID CallingConv;
bool IsVarArg;
const TargetMachine &TM;
- const TargetRegisterInfo &TRI;
SmallVector<CCValAssign, 16> &Locs;
LLVMContext &Context;