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authorAlp Toker <alp@nuanti.com>2014-01-24 17:20:08 +0000
committerAlp Toker <alp@nuanti.com>2014-01-24 17:20:08 +0000
commitae43cab6bab0e5bcdbe2971bf718712559625e39 (patch)
tree536b346c514acfc8d7f3c2e424e1295de63e516a /lib/Target/Hexagon/HexagonHardwareLoops.cpp
parent27ce8feb4adbb13c0efcc2d560c93dfb71785cb2 (diff)
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Fix known typos
Sweep the codebase for common typos. Includes some changes to visible function names that were misspelt. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@200018 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/Hexagon/HexagonHardwareLoops.cpp')
-rw-r--r--lib/Target/Hexagon/HexagonHardwareLoops.cpp4
1 files changed, 2 insertions, 2 deletions
diff --git a/lib/Target/Hexagon/HexagonHardwareLoops.cpp b/lib/Target/Hexagon/HexagonHardwareLoops.cpp
index 137c4bf054..fccbcb3d70 100644
--- a/lib/Target/Hexagon/HexagonHardwareLoops.cpp
+++ b/lib/Target/Hexagon/HexagonHardwareLoops.cpp
@@ -1522,7 +1522,7 @@ MachineBasicBlock *HexagonHardwareLoops::createPreheaderForLoop(
if (PB != Latch) {
Tmp2.clear();
bool NotAnalyzed = TII->AnalyzeBranch(*PB, TB, FB, Tmp2, false);
- (void)NotAnalyzed; // supress compiler warning
+ (void)NotAnalyzed; // suppress compiler warning
assert (!NotAnalyzed && "Should be analyzable!");
if (TB != Header && (Tmp2.empty() || FB != Header))
TII->InsertBranch(*PB, NewPH, 0, EmptyCond, DL);
@@ -1534,7 +1534,7 @@ MachineBasicBlock *HexagonHardwareLoops::createPreheaderForLoop(
// Insert an unconditional branch to the header.
TB = FB = 0;
bool LatchNotAnalyzed = TII->AnalyzeBranch(*Latch, TB, FB, Tmp2, false);
- (void)LatchNotAnalyzed; // supress compiler warning
+ (void)LatchNotAnalyzed; // suppress compiler warning
assert (!LatchNotAnalyzed && "Should be analyzable!");
if (!TB && !FB)
TII->InsertBranch(*Latch, Header, 0, EmptyCond, DL);