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| author | Andrew Trick <atrick@apple.com> | 2013-05-25 02:42:55 +0000 |
|---|---|---|
| committer | Andrew Trick <atrick@apple.com> | 2013-05-25 02:42:55 +0000 |
| commit | ac6d9bec671252dd1e596fa71180ff6b39d06b5d (patch) | |
| tree | 414f60df511ae112e9498df4f722cb1a9ee2fbba /lib/Target/Hexagon/HexagonISelLowering.h | |
| parent | ea5db0c315f1ab8ee3be52e0e765c32d3efff024 (diff) | |
| download | llvm-ac6d9bec671252dd1e596fa71180ff6b39d06b5d.tar.gz llvm-ac6d9bec671252dd1e596fa71180ff6b39d06b5d.tar.bz2 llvm-ac6d9bec671252dd1e596fa71180ff6b39d06b5d.tar.xz | |
Track IR ordering of SelectionDAG nodes 2/4.
Change SelectionDAG::getXXXNode() interfaces as well as call sites of
these functions to pass in SDLoc instead of DebugLoc.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182703 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/Hexagon/HexagonISelLowering.h')
| -rw-r--r-- | lib/Target/Hexagon/HexagonISelLowering.h | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/lib/Target/Hexagon/HexagonISelLowering.h b/lib/Target/Hexagon/HexagonISelLowering.h index 3045905076..70642e6af5 100644 --- a/lib/Target/Hexagon/HexagonISelLowering.h +++ b/lib/Target/Hexagon/HexagonISelLowering.h @@ -106,7 +106,7 @@ namespace llvm { SDValue LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl<ISD::InputArg> &Ins, - DebugLoc dl, SelectionDAG &DAG, + SDLoc dl, SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const; SDValue LowerGLOBALADDRESS(SDValue Op, SelectionDAG &DAG) const; SDValue LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const; @@ -117,7 +117,7 @@ namespace llvm { SDValue LowerCallResult(SDValue Chain, SDValue InFlag, CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl<ISD::InputArg> &Ins, - DebugLoc dl, SelectionDAG &DAG, + SDLoc dl, SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals, const SmallVectorImpl<SDValue> &OutVals, SDValue Callee) const; @@ -131,7 +131,7 @@ namespace llvm { CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl<ISD::OutputArg> &Outs, const SmallVectorImpl<SDValue> &OutVals, - DebugLoc dl, SelectionDAG &DAG) const; + SDLoc dl, SelectionDAG &DAG) const; virtual MachineBasicBlock *EmitInstrWithCustomInserter(MachineInstr *MI, |