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| author | Sirish Pande <spande@codeaurora.org> | 2012-05-10 20:20:25 +0000 |
|---|---|---|
| committer | Sirish Pande <spande@codeaurora.org> | 2012-05-10 20:20:25 +0000 |
| commit | 7517bbc91ae1c60d3c7df8b11642c7a5bb3d5a71 (patch) | |
| tree | 8a348ecf53f5f593b3198b96ffa4df264eadbe43 /lib/Target/Hexagon/HexagonInstrInfo.cpp | |
| parent | 55ba5dff3c1a723adf302f1124aafde797dbf31a (diff) | |
| download | llvm-7517bbc91ae1c60d3c7df8b11642c7a5bb3d5a71.tar.gz llvm-7517bbc91ae1c60d3c7df8b11642c7a5bb3d5a71.tar.bz2 llvm-7517bbc91ae1c60d3c7df8b11642c7a5bb3d5a71.tar.xz | |
Hexagon V5 FP Support.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156568 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/Hexagon/HexagonInstrInfo.cpp')
| -rw-r--r-- | lib/Target/Hexagon/HexagonInstrInfo.cpp | 23 |
1 files changed, 18 insertions, 5 deletions
diff --git a/lib/Target/Hexagon/HexagonInstrInfo.cpp b/lib/Target/Hexagon/HexagonInstrInfo.cpp index 655ddbce8f..8286ca93f2 100644 --- a/lib/Target/Hexagon/HexagonInstrInfo.cpp +++ b/lib/Target/Hexagon/HexagonInstrInfo.cpp @@ -444,14 +444,15 @@ unsigned HexagonInstrInfo::createVR(MachineFunction* MF, MVT VT) const { MachineRegisterInfo &RegInfo = MF->getRegInfo(); const TargetRegisterClass *TRC; - if (VT == MVT::i1) + if (VT == MVT::i1) { TRC = &Hexagon::PredRegsRegClass; - else if (VT == MVT::i32) + } else if (VT == MVT::i32 || VT == MVT::f32) { TRC = &Hexagon::IntRegsRegClass; - else if (VT == MVT::i64) + } else if (VT == MVT::i64 || VT == MVT::f64) { TRC = &Hexagon::DoubleRegsRegClass; - else + } else { llvm_unreachable("Cannot handle this register class"); + } unsigned NewReg = RegInfo.createVirtualRegister(TRC); return NewReg; @@ -714,8 +715,13 @@ bool HexagonInstrInfo::isExtended(const MachineInstr *MI) const { // TFR_FI case Hexagon::TFR_FI_immext_V4: - return true; + // TFRI_F + case Hexagon::TFRI_f: + case Hexagon::TFRI_cPt_f: + case Hexagon::TFRI_cNotPt_f: + case Hexagon::CONST64_Float_Real: + return true; } } @@ -1892,6 +1898,9 @@ getMatchingCondBranchOpcode(int Opc, bool invertPredicate) const { case Hexagon::TFR: return !invertPredicate ? Hexagon::TFR_cPt : Hexagon::TFR_cNotPt; + case Hexagon::TFRI_f: + return !invertPredicate ? Hexagon::TFRI_cPt_f : + Hexagon::TFRI_cNotPt_f; case Hexagon::TFRI: return !invertPredicate ? Hexagon::TFRI_cPt : Hexagon::TFRI_cNotPt; @@ -2330,13 +2339,17 @@ isValidOffset(const int Opcode, const int Offset) const { switch(Opcode) { case Hexagon::LDriw: + case Hexagon::LDriw_f: case Hexagon::STriw: + case Hexagon::STriw_f: assert((Offset % 4 == 0) && "Offset has incorrect alignment"); return (Offset >= Hexagon_MEMW_OFFSET_MIN) && (Offset <= Hexagon_MEMW_OFFSET_MAX); case Hexagon::LDrid: + case Hexagon::LDrid_f: case Hexagon::STrid: + case Hexagon::STrid_f: assert((Offset % 8 == 0) && "Offset has incorrect alignment"); return (Offset >= Hexagon_MEMD_OFFSET_MIN) && (Offset <= Hexagon_MEMD_OFFSET_MAX); |