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| author | Justin Holewinski <jholewinski@nvidia.com> | 2013-02-12 14:18:49 +0000 |
|---|---|---|
| committer | Justin Holewinski <jholewinski@nvidia.com> | 2013-02-12 14:18:49 +0000 |
| commit | 7eacad03efda36e09ebd96e95d7891cadaaa9087 (patch) | |
| tree | c66658286eca956701f8334550a8edefe236b468 /lib/Target/Hexagon/HexagonInstrInfo.cpp | |
| parent | c8a196ae8fad3cba7a777e2e7916fd36ebf70fe6 (diff) | |
| download | llvm-7eacad03efda36e09ebd96e95d7891cadaaa9087.tar.gz llvm-7eacad03efda36e09ebd96e95d7891cadaaa9087.tar.bz2 llvm-7eacad03efda36e09ebd96e95d7891cadaaa9087.tar.xz | |
[NVPTX] Disable vector registers
Vectors were being manually scalarized by the backend. Instead,
let the target-independent code do all of the work. The manual
scalarization was from a time before good target-independent support
for scalarization in LLVM. However, this forces us to specially-handle
vector loads and stores, which we can turn into PTX instructions that
produce/consume multiple operands.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174968 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/Hexagon/HexagonInstrInfo.cpp')
0 files changed, 0 insertions, 0 deletions