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| author | Sirish Pande <spande@codeaurora.org> | 2012-04-23 17:49:40 +0000 |
|---|---|---|
| committer | Sirish Pande <spande@codeaurora.org> | 2012-04-23 17:49:40 +0000 |
| commit | 15e56ad8855ff2d135a79efa71b540852acf3b97 (patch) | |
| tree | 413596c80d7451183d7eecb7be0d3042d605d1c6 /lib/Target/Hexagon/HexagonInstrInfo.h | |
| parent | 1bfd24851ef35e754d9652551e1a7abb12fe6738 (diff) | |
| download | llvm-15e56ad8855ff2d135a79efa71b540852acf3b97.tar.gz llvm-15e56ad8855ff2d135a79efa71b540852acf3b97.tar.bz2 llvm-15e56ad8855ff2d135a79efa71b540852acf3b97.tar.xz | |
Hexagon V5 (floating point) support.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155367 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/Hexagon/HexagonInstrInfo.h')
| -rw-r--r-- | lib/Target/Hexagon/HexagonInstrInfo.h | 23 |
1 files changed, 12 insertions, 11 deletions
diff --git a/lib/Target/Hexagon/HexagonInstrInfo.h b/lib/Target/Hexagon/HexagonInstrInfo.h index 1f2c6cbfa5..9682c05ea1 100644 --- a/lib/Target/Hexagon/HexagonInstrInfo.h +++ b/lib/Target/Hexagon/HexagonInstrInfo.h @@ -107,6 +107,8 @@ public: unsigned createVR(MachineFunction* MF, MVT VT) const; + virtual bool isExtendable(const MachineInstr* MI) const; + virtual bool isExtended(const MachineInstr* MI) const; virtual bool isPredicable(MachineInstr *MI) const; virtual bool PredicateInstruction(MachineInstr *MI, @@ -136,6 +138,10 @@ public: isProfitableToDupForIfCvt(MachineBasicBlock &MBB,unsigned NumCycles, const BranchProbability &Probability) const; + unsigned getInvertedPredicatedOpcode(const int Opcode) const; + unsigned getImmExtForm(const MachineInstr* MI) const; + unsigned getNormalBranchForm(const MachineInstr* MI) const; + virtual DFAPacketizer* CreateTargetScheduleState(const TargetMachine *TM, const ScheduleDAG *DAG) const; @@ -160,21 +166,16 @@ public: bool isS8_Immediate(const int value) const; bool isS6_Immediate(const int value) const; - bool isSaveCalleeSavedRegsCall(const MachineInstr* MI) const; bool isConditionalTransfer(const MachineInstr* MI) const; - bool isConditionalALU32 (const MachineInstr* MI) const; - bool isConditionalLoad (const MachineInstr* MI) const; + bool isConditionalALU32(const MachineInstr* MI) const; + bool isConditionalLoad(const MachineInstr* MI) const; bool isConditionalStore(const MachineInstr* MI) const; bool isDeallocRet(const MachineInstr *MI) const; - unsigned getInvertedPredicatedOpcode(const int Opc) const; - bool isExtendable(const MachineInstr* MI) const; - bool isExtended(const MachineInstr* MI) const; - bool isPostIncrement(const MachineInstr* MI) const; - bool isNewValueStore(const MachineInstr* MI) const; - bool isNewValueJump(const MachineInstr* MI) const; bool isNewValueJumpCandidate(const MachineInstr *MI) const; - unsigned getImmExtForm(const MachineInstr* MI) const; - unsigned getNormalBranchForm(const MachineInstr* MI) const; + bool isNewValueJump(const MachineInstr* MI) const; + bool isNewValueStore(const MachineInstr* MI) const; + bool isPostIncrement(const MachineInstr* MI) const; + bool isSaveCalleeSavedRegsCall(const MachineInstr* MI) const; private: int getMatchingCondBranchOpcode(int Opc, bool sense) const; |