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| author | Jyotsna Verma <jverma@codeaurora.org> | 2014-05-07 19:07:34 +0000 |
|---|---|---|
| committer | Jyotsna Verma <jverma@codeaurora.org> | 2014-05-07 19:07:34 +0000 |
| commit | 8b915bad69dae9213bde4c49c1657790c32d4911 (patch) | |
| tree | 82e2a8f84f778049cff7c58d12b8b7e3e8af2f36 /lib/Target/Hexagon/HexagonInstrInfo.td | |
| parent | 4842e7db63524f1ab4e313cea7b443908ebdf6dc (diff) | |
| download | llvm-8b915bad69dae9213bde4c49c1657790c32d4911.tar.gz llvm-8b915bad69dae9213bde4c49c1657790c32d4911.tar.bz2 llvm-8b915bad69dae9213bde4c49c1657790c32d4911.tar.xz | |
[Hexagon] Add New TSFlags to be used in the upcoming patches.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208239 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/Hexagon/HexagonInstrInfo.td')
| -rw-r--r-- | lib/Target/Hexagon/HexagonInstrInfo.td | 14 |
1 files changed, 8 insertions, 6 deletions
diff --git a/lib/Target/Hexagon/HexagonInstrInfo.td b/lib/Target/Hexagon/HexagonInstrInfo.td index c96aaca8f8..4dcf101ea3 100644 --- a/lib/Target/Hexagon/HexagonInstrInfo.td +++ b/lib/Target/Hexagon/HexagonInstrInfo.td @@ -768,12 +768,13 @@ class T_JMP <dag InsDag, list<dag> JumpList = []> let InputType = "imm", isExtendable = 1, opExtendable = 1, isExtentSigned = 1, Defs = [PC], isPredicated = 1, opExtentBits = 17 in -class T_JMP_c <bit PredNot, bit isPredNew, bit isTaken>: +class T_JMP_c <bit PredNot, bit isPredNew, bit isTak>: JInst<(outs ), (ins PredRegs:$src, brtarget:$dst), !if(PredNot, "if (!$src", "if ($src")# !if(isPredNew, ".new) ", ") ")#"jump"# - !if(isPredNew, !if(isTaken, ":t ", ":nt "), " ")#"$dst"> { + !if(isPredNew, !if(isTak, ":t ", ":nt "), " ")#"$dst"> { + let isTaken = isTak; let isBrTaken = !if(isPredNew, !if(isTaken, "true", "false"), ""); let isPredicatedFalse = PredNot; let isPredicatedNew = isPredNew; @@ -784,7 +785,7 @@ class T_JMP_c <bit PredNot, bit isPredNew, bit isTaken>: let Inst{27-24} = 0b1100; let Inst{21} = PredNot; - let Inst{12} = !if(isPredNew, isTaken, zero); + let Inst{12} = !if(isPredNew, isTak, zero); let Inst{11} = isPredNew; let Inst{9-8} = src; let Inst{23-22} = dst{16-15}; @@ -806,12 +807,13 @@ class T_JMPr<dag InsDag = (ins IntRegs:$dst)> } let Defs = [PC], isPredicated = 1, InputType = "reg" in -class T_JMPr_c <bit PredNot, bit isPredNew, bit isTaken>: +class T_JMPr_c <bit PredNot, bit isPredNew, bit isTak>: JRInst <(outs ), (ins PredRegs:$src, IntRegs:$dst), !if(PredNot, "if (!$src", "if ($src")# !if(isPredNew, ".new) ", ") ")#"jumpr"# - !if(isPredNew, !if(isTaken, ":t ", ":nt "), " ")#"$dst"> { + !if(isPredNew, !if(isTak, ":t ", ":nt "), " ")#"$dst"> { + let isTaken = isTak; let isBrTaken = !if(isPredNew, !if(isTaken, "true", "false"), ""); let isPredicatedFalse = PredNot; let isPredicatedNew = isPredNew; @@ -823,7 +825,7 @@ class T_JMPr_c <bit PredNot, bit isPredNew, bit isTaken>: let Inst{27-22} = 0b001101; let Inst{21} = PredNot; let Inst{20-16} = dst; - let Inst{12} = !if(isPredNew, isTaken, zero); + let Inst{12} = !if(isPredNew, isTak, zero); let Inst{11} = isPredNew; let Inst{9-8} = src; let Predicates = !if(isPredNew, [HasV3T], [HasV2T]); |