Revert r155365, r155366, and r155367. All three of these have regression

test suite failures. The failures occur at each stage, and only get
worse, so I'm reverting all of them.

Please resubmit these patches, one at a time, after verifying that the
regression test suite passes. Never submit a patch without running the
regression test suite.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155372 91177308-0d34-0410-b5e6-96231b3b80d8

1 files changed, 24 insertions, 27 deletions

diff --git a/lib/Target/Hexagon/HexagonInstrInfoV3.td b/lib/Target/Hexagon/HexagonInstrInfoV3.td
index 2bd6770efd..a73897ee34 100644
--- a/lib/Target/Hexagon/HexagonInstrInfoV3.td
+++ b/lib/Target/Hexagon/HexagonInstrInfoV3.td
@@ -41,11 +41,10 @@ let isCall = 1, neverHasSideEffects = 1,
  }
 
 
-// Jump to address from register
 // if(p?.new) jumpr:t r?
 let isReturn = 1, isTerminator = 1, isBarrier = 1,
   Defs = [PC], Uses = [R31] in {
-  def JMPR_cdnPt_V3: JRInst<(outs), (ins PredRegs:$src1, IntRegs:$src2),
+  def JMPR_cPnewt: JRInst<(outs), (ins PredRegs:$src1, IntRegs:$src2),
                        "if ($src1.new) jumpr:t $src2",
                        []>, Requires<[HasV3T]>;
 }
@@ -53,7 +52,7 @@ let isReturn = 1, isTerminator = 1, isBarrier = 1,
 // if (!p?.new) jumpr:t r?
 let isReturn = 1, isTerminator = 1, isBarrier = 1,
   Defs = [PC], Uses = [R31] in {
-  def JMPR_cdnNotPt_V3: JRInst<(outs), (ins PredRegs:$src1, IntRegs:$src2),
+  def JMPR_cNotPnewt: JRInst<(outs), (ins PredRegs:$src1, IntRegs:$src2),
                        "if (!$src1.new) jumpr:t $src2",
                        []>, Requires<[HasV3T]>;
 }
@@ -62,7 +61,7 @@ let isReturn = 1, isTerminator = 1, isBarrier = 1,
 // if(p?.new) jumpr:nt r?
 let isReturn = 1, isTerminator = 1, isBarrier = 1,
   Defs = [PC], Uses = [R31] in {
-  def JMPR_cdnPnt: JRInst<(outs), (ins PredRegs:$src1, IntRegs:$src2),
+  def JMPR_cPnewNt: JRInst<(outs), (ins PredRegs:$src1, IntRegs:$src2),
                        "if ($src1.new) jumpr:nt $src2",
                        []>, Requires<[HasV3T]>;
 }
@@ -70,7 +69,7 @@ let isReturn = 1, isTerminator = 1, isBarrier = 1,
 // if (!p?.new) jumpr:nt r?
 let isReturn = 1, isTerminator = 1, isBarrier = 1,
   Defs = [PC], Uses = [R31] in {
-  def JMPR_cdnNotPnt: JRInst<(outs), (ins PredRegs:$src1, IntRegs:$src2),
+  def JMPR_cNotPnewNt: JRInst<(outs), (ins PredRegs:$src1, IntRegs:$src2),
                        "if (!$src1.new) jumpr:nt $src2",
                        []>, Requires<[HasV3T]>;
 }
@@ -87,22 +86,20 @@ let AddedComplexity = 200 in
 def MAXw_dd : ALU64_rr<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1,
                                                     DoubleRegs:$src2),
               "$dst = max($src2, $src1)",
-              [(set (i64 DoubleRegs:$dst),
-                    (i64 (select (i1 (setlt (i64 DoubleRegs:$src2),
-                                            (i64 DoubleRegs:$src1))),
-                                 (i64 DoubleRegs:$src1),
-                                 (i64 DoubleRegs:$src2))))]>,
+              [(set DoubleRegs:$dst, (select (i1 (setlt DoubleRegs:$src2,
+                                                        DoubleRegs:$src1)),
+                                             DoubleRegs:$src1,
+                                             DoubleRegs:$src2))]>,
 Requires<[HasV3T]>;
 
 let AddedComplexity = 200 in
 def MINw_dd : ALU64_rr<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1,
                                                     DoubleRegs:$src2),
               "$dst = min($src2, $src1)",
-              [(set (i64 DoubleRegs:$dst),
-                    (i64 (select (i1 (setgt (i64 DoubleRegs:$src2),
-                                            (i64 DoubleRegs:$src1))),
-                                 (i64 DoubleRegs:$src1),
-                                 (i64 DoubleRegs:$src2))))]>,
+              [(set DoubleRegs:$dst, (select (i1 (setgt DoubleRegs:$src2,
+                                                        DoubleRegs:$src1)),
+                                             DoubleRegs:$src1,
+                                             DoubleRegs:$src2))]>,
 Requires<[HasV3T]>;
 
 //===----------------------------------------------------------------------===//
@@ -112,25 +109,25 @@ Requires<[HasV3T]>;
 
 
 
-//def : Pat <(brcond (i1 (seteq (i32 IntRegs:$src1), 0)), bb:$offset),
-//      (JMP_RegEzt (i32 IntRegs:$src1), bb:$offset)>, Requires<[HasV3T]>;
+//def : Pat <(brcond (i1 (seteq IntRegs:$src1, 0)), bb:$offset),
+//      (JMP_RegEzt IntRegs:$src1, bb:$offset)>, Requires<[HasV3T]>;
 
-//def : Pat <(brcond (i1 (setne (i32 IntRegs:$src1), 0)), bb:$offset),
-//      (JMP_RegNzt (i32 IntRegs:$src1), bb:$offset)>, Requires<[HasV3T]>;
+//def : Pat <(brcond (i1 (setne IntRegs:$src1, 0)), bb:$offset),
+//      (JMP_RegNzt IntRegs:$src1, bb:$offset)>, Requires<[HasV3T]>;
 
-//def : Pat <(brcond (i1 (setle (i32 IntRegs:$src1), 0)), bb:$offset),
-//      (JMP_RegLezt (i32 IntRegs:$src1), bb:$offset)>, Requires<[HasV3T]>;
+//def : Pat <(brcond (i1 (setle IntRegs:$src1, 0)), bb:$offset),
+//      (JMP_RegLezt IntRegs:$src1, bb:$offset)>, Requires<[HasV3T]>;
 
-//def : Pat <(brcond (i1 (setge (i32 IntRegs:$src1), 0)), bb:$offset),
-//      (JMP_RegGezt (i32 IntRegs:$src1), bb:$offset)>, Requires<[HasV3T]>;
+//def : Pat <(brcond (i1 (setge IntRegs:$src1, 0)), bb:$offset),
+//      (JMP_RegGezt IntRegs:$src1, bb:$offset)>, Requires<[HasV3T]>;
 
-//def : Pat <(brcond (i1 (setgt (i32 IntRegs:$src1), -1)), bb:$offset),
-//      (JMP_RegGezt (i32 IntRegs:$src1), bb:$offset)>, Requires<[HasV3T]>;
+//def : Pat <(brcond (i1 (setgt IntRegs:$src1, -1)), bb:$offset),
+//      (JMP_RegGezt IntRegs:$src1, bb:$offset)>, Requires<[HasV3T]>;
 
 
 // Map call instruction
-def : Pat<(call (i32 IntRegs:$dst)),
-      (CALLRv3 (i32 IntRegs:$dst))>, Requires<[HasV3T]>;
+def : Pat<(call IntRegs:$dst),
+      (CALLRv3 IntRegs:$dst)>, Requires<[HasV3T]>;
 def : Pat<(call tglobaladdr:$dst),
       (CALLv3 tglobaladdr:$dst)>, Requires<[HasV3T]>;
 def : Pat<(call texternalsym:$dst),