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| author | Jyotsna Verma <jverma@codeaurora.org> | 2013-04-23 21:05:55 +0000 |
|---|---|---|
| committer | Jyotsna Verma <jverma@codeaurora.org> | 2013-04-23 21:05:55 +0000 |
| commit | 197c833ee142e9e7c78fa0b667f16cdb09e6f6b5 (patch) | |
| tree | 037026f54fd23eb8aff1f099ae79c0f58bdba665 /lib/Target/Hexagon/HexagonInstrInfoV4.td | |
| parent | f48509787acfcfc3f9eee2fb3084c2e8c7b4a009 (diff) | |
| download | llvm-197c833ee142e9e7c78fa0b667f16cdb09e6f6b5.tar.gz llvm-197c833ee142e9e7c78fa0b667f16cdb09e6f6b5.tar.bz2 llvm-197c833ee142e9e7c78fa0b667f16cdb09e6f6b5.tar.xz | |
Hexagon: Define relations for GP-relative instructions.
No functionality change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180144 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/Hexagon/HexagonInstrInfoV4.td')
| -rw-r--r-- | lib/Target/Hexagon/HexagonInstrInfoV4.td | 32 |
1 files changed, 17 insertions, 15 deletions
diff --git a/lib/Target/Hexagon/HexagonInstrInfoV4.td b/lib/Target/Hexagon/HexagonInstrInfoV4.td index ef89e8bfdf..6c3dfd9052 100644 --- a/lib/Target/Hexagon/HexagonInstrInfoV4.td +++ b/lib/Target/Hexagon/HexagonInstrInfoV4.td @@ -2755,6 +2755,7 @@ def : Pat<(store (i64 DoubleRegs:$src1), // mem[bhwd](#global)=Rt // if ([!]Pv[.new]) mem[bhwd](##global) = Rt //===----------------------------------------------------------------------===// +let mayStore = 1, isNVStorable = 1 in multiclass ST_GP<string mnemonic, string BaseOp, RegisterClass RC> { let BaseOpcode = BaseOp, isPredicable = 1 in def NAME#_V4 : STInst2<(outs), @@ -2789,15 +2790,16 @@ multiclass ST_GP_nv<string mnemonic, string BaseOp, RegisterClass RC> { } } -let validSubTargets = HasV4SubT, validSubTargets = HasV4SubT in { -defm STd_GP : ST_GP <"memd", "STd_GP", DoubleRegs>, - ST_GP_nv<"memd", "STd_GP", DoubleRegs>, NewValueRel ; -defm STb_GP : ST_GP<"memb", "STb_GP", IntRegs>, - ST_GP_nv<"memb", "STb_GP", IntRegs>, NewValueRel ; -defm STh_GP : ST_GP<"memh", "STh_GP", IntRegs>, - ST_GP_nv<"memh", "STh_GP", IntRegs>, NewValueRel ; -defm STw_GP : ST_GP<"memw", "STw_GP", IntRegs>, - ST_GP_nv<"memw", "STw_GP", IntRegs>, NewValueRel ; +let validSubTargets = HasV4SubT, neverHasSideEffects = 1 in { + let isNVStorable = 0 in + defm STd_GP : ST_GP <"memd", "STd_GP", DoubleRegs>, PredNewRel; + + defm STb_GP : ST_GP<"memb", "STb_GP", IntRegs>, + ST_GP_nv<"memb", "STb_GP", IntRegs>, NewValueRel; + defm STh_GP : ST_GP<"memh", "STh_GP", IntRegs>, + ST_GP_nv<"memh", "STh_GP", IntRegs>, NewValueRel; + defm STw_GP : ST_GP<"memw", "STw_GP", IntRegs>, + ST_GP_nv<"memw", "STw_GP", IntRegs>, NewValueRel; } // 64 bit atomic store @@ -2942,12 +2944,12 @@ multiclass LD_GP<string mnemonic, string BaseOp, RegisterClass RC> { } } -defm LDd_GP : LD_GP<"memd", "LDd_GP", DoubleRegs>; -defm LDb_GP : LD_GP<"memb", "LDb_GP", IntRegs>; -defm LDub_GP : LD_GP<"memub", "LDub_GP", IntRegs>; -defm LDh_GP : LD_GP<"memh", "LDh_GP", IntRegs>; -defm LDuh_GP : LD_GP<"memuh", "LDuh_GP", IntRegs>; -defm LDw_GP : LD_GP<"memw", "LDw_GP", IntRegs>; +defm LDd_GP : LD_GP<"memd", "LDd_GP", DoubleRegs>, PredNewRel; +defm LDb_GP : LD_GP<"memb", "LDb_GP", IntRegs>, PredNewRel; +defm LDub_GP : LD_GP<"memub", "LDub_GP", IntRegs>, PredNewRel; +defm LDh_GP : LD_GP<"memh", "LDh_GP", IntRegs>, PredNewRel; +defm LDuh_GP : LD_GP<"memuh", "LDuh_GP", IntRegs>, PredNewRel; +defm LDw_GP : LD_GP<"memw", "LDw_GP", IntRegs>, PredNewRel; def : Pat <(atomic_load_64 (HexagonCONST32_GP tglobaladdr:$global)), (i64 (LDd_GP_V4 tglobaladdr:$global))>; |