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author | Tim Northover <tnorthover@apple.com> | 2014-05-20 11:52:46 +0000 |
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committer | Tim Northover <tnorthover@apple.com> | 2014-05-20 11:52:46 +0000 |
commit | ee8d5c393ef04bbf19cb5aa9460ebb054e60fa3e (patch) | |
tree | c400e0f76859c04cf9c7af02d6b126bee1b8b59c /lib/Target/Hexagon/HexagonInstrInfoV4.td | |
parent | 57a98baa07ae4b4bd9d7702afc81f95b93abb48d (diff) | |
download | llvm-ee8d5c393ef04bbf19cb5aa9460ebb054e60fa3e.tar.gz llvm-ee8d5c393ef04bbf19cb5aa9460ebb054e60fa3e.tar.bz2 llvm-ee8d5c393ef04bbf19cb5aa9460ebb054e60fa3e.tar.xz |
TableGen: permit non-leaf ComplexPattern uses
This allows the results of a ComplexPattern check to be distributed to separate
named Operands, instead of the current system where all results must apply (and
match perfectly) with a single Operand.
For example, if "some_addrmode" is a ComplexPattern producing two results, you
can write:
def : Pat<(load (some_addrmode GPR64:$base, imm:$offset)),
(INST GPR64:$base, imm:$offset)>;
This should allow neater instruction definitions in TableGen that don't put all
possible aspects of addressing into a single operand, but are still usable with
relatively simple C++ CodeGen idioms.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209206 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/Hexagon/HexagonInstrInfoV4.td')
-rw-r--r-- | lib/Target/Hexagon/HexagonInstrInfoV4.td | 14 |
1 files changed, 8 insertions, 6 deletions
diff --git a/lib/Target/Hexagon/HexagonInstrInfoV4.td b/lib/Target/Hexagon/HexagonInstrInfoV4.td index 2c0ce11fe8..db5b7eaa68 100644 --- a/lib/Target/Hexagon/HexagonInstrInfoV4.td +++ b/lib/Target/Hexagon/HexagonInstrInfoV4.td @@ -2022,9 +2022,10 @@ multiclass MemOpi_bitPats <PatFrag ldOp, PatFrag stOp, PatLeaf immPred, // mem[bhw](Rs+#0) = [clrbit|setbit](#U5) let AddedComplexity = 225 in - def : Pat <(stOp (OpNode (ldOp addrPred:$addr), immPred:$bitend), - addrPred:$addr), - (MI IntRegs:$addr, #0, (xformFunc immPred:$bitend))>; + def : Pat <(stOp (OpNode (ldOp (addrPred IntRegs:$addr, extPred:$offset)), + immPred:$bitend), + (addrPred (i32 IntRegs:$addr), extPred:$offset)), + (MI IntRegs:$addr, extPred:$offset, (xformFunc immPred:$bitend))>; } multiclass MemOpi_bitExtType<PatFrag ldOpByte, PatFrag ldOpHalf > { @@ -2068,9 +2069,10 @@ multiclass MemOpr_Pats <PatFrag ldOp, PatFrag stOp, ComplexPattern addrPred, PatLeaf extPred, InstHexagon MI, SDNode OpNode> { let AddedComplexity = 141 in // mem[bhw](Rs+#0) [+-&|]= Rt - def : Pat <(stOp (OpNode (ldOp addrPred:$addr), (i32 IntRegs:$addend)), - addrPred:$addr), - (MI IntRegs:$addr, #0, (i32 IntRegs:$addend) )>; + def : Pat <(stOp (OpNode (ldOp (addrPred IntRegs:$addr, extPred:$offset)), + (i32 IntRegs:$addend)), + (addrPred (i32 IntRegs:$addr), extPred:$offset)), + (MI IntRegs:$addr, extPred:$offset, (i32 IntRegs:$addend) )>; // mem[bhw](Rs+#U6:[012]) [+-&|]= Rt let AddedComplexity = 150 in |