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authorCraig Topper <craig.topper@gmail.com>2012-04-13 06:38:11 +0000
committerCraig Topper <craig.topper@gmail.com>2012-04-13 06:38:11 +0000
commit7a2e472d527156165273a6c105ca7a93ff9e48f8 (patch)
tree00c5aff3d4ff48220ad7c8580adcb1ca2560d580 /lib/Target/Hexagon/HexagonVLIWPacketizer.cpp
parentb57b170317f12370183111fc458de3352c5f71dc (diff)
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Silence various build warnings from Hexagon backend that show up in release builds. Mostly converting 'assert(0)' to 'llvm_unreachable' to silence warnings about missing returns. Also fold some variable declarations into asserts to prevent the variables from being unused in release builds.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154660 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/Hexagon/HexagonVLIWPacketizer.cpp')
-rw-r--r--lib/Target/Hexagon/HexagonVLIWPacketizer.cpp36
1 files changed, 12 insertions, 24 deletions
diff --git a/lib/Target/Hexagon/HexagonVLIWPacketizer.cpp b/lib/Target/Hexagon/HexagonVLIWPacketizer.cpp
index 0fe97ef5f7..c6e7bd1f53 100644
--- a/lib/Target/Hexagon/HexagonVLIWPacketizer.cpp
+++ b/lib/Target/Hexagon/HexagonVLIWPacketizer.cpp
@@ -102,7 +102,7 @@ namespace {
MachineDominatorTree &MDT);
// initPacketizerState - initialize some internal flags.
- void initPacketizerState(void);
+ void initPacketizerState();
// ignorePseudoInstruction - Ignore bundling of pseudo instructions.
bool ignorePseudoInstruction(MachineInstr *MI, MachineBasicBlock *MBB);
@@ -250,7 +250,7 @@ void HexagonPacketizerList::reserveResourcesForConstExt(MachineInstr* MI) {
MI->getParent()->getParent()->DeleteMachineInstr(PseudoMI);
} else {
MI->getParent()->getParent()->DeleteMachineInstr(PseudoMI);
- assert(0 && "can not reserve resources for constant extender.");
+ llvm_unreachable("can not reserve resources for constant extender.");
}
return;
}
@@ -491,6 +491,7 @@ static bool DoesModifyCalleeSavedReg(MachineInstr *MI,
// Return the new value instruction for a given store.
static int GetDotNewOp(const int opc) {
switch (opc) {
+ default: llvm_unreachable("Unknown .new type");
// store new value byte
case Hexagon::STrib:
@@ -773,16 +774,14 @@ static int GetDotNewOp(const int opc) {
case Hexagon::STriw_GP_cdnNotPt_V4:
return Hexagon::STriw_GP_cdnNotPt_nv_V4;
-
- default:
- assert(0 && "Unknown .new type");
}
- return 0;
}
// Return .new predicate version for an instruction
static int GetDotNewPredOp(const int opc) {
switch (opc) {
+ default: llvm_unreachable("Unknown .new type");
+
// Conditional stores
// Store byte conditionally
case Hexagon::STrib_cPt :
@@ -1405,12 +1404,7 @@ static int GetDotNewPredOp(const int opc) {
return Hexagon::ZXTH_cdnPt_V4;
case Hexagon::ZXTH_cNotPt_V4 :
return Hexagon::ZXTH_cdnNotPt_V4;
-
-
- default:
- assert(0 && "Unknown .new type");
}
- return 0;
}
// Returns true if an instruction can be promoted to .new predicate
@@ -1482,6 +1476,8 @@ bool HexagonPacketizerList::PromoteToDotNew(MachineInstr* MI,
static int GetDotOldOp(const int opc) {
switch (opc) {
+ default: llvm_unreachable("Unknown .old type");
+
case Hexagon::TFR_cdnPt:
return Hexagon::TFR_cPt;
@@ -2156,11 +2152,7 @@ static int GetDotOldOp(const int opc) {
case Hexagon::STrid_GP_cdnNotPt_V4 :
return Hexagon::STrid_GP_cNotPt_V4;
-
- default:
- assert(0 && "Unknown .old type");
}
- return 0;
}
bool HexagonPacketizerList::DemoteToDotOld(MachineInstr* MI) {
@@ -2761,10 +2753,7 @@ static MachineOperand& GetPostIncrementOperand(MachineInstr *MI,
}
#endif
// we should never come here.
- assert(0 && "mayLoad or mayStore not set for Post Increment operation");
-
- // return *some value* to avoid compiler warning
- return MI->getOperand(0);
+ llvm_unreachable("mayLoad or mayStore not set for Post Increment operation");
}
// get the value being stored
@@ -3167,7 +3156,7 @@ bool HexagonPacketizerList::ArePredicatesComplements (MachineInstr* MI1,
}
// initPacketizerState - Initialize packetizer flags
-void HexagonPacketizerList::initPacketizerState(void) {
+void HexagonPacketizerList::initPacketizerState() {
Dependence = false;
PromotedToDotNew = false;
@@ -3236,10 +3225,10 @@ bool HexagonPacketizerList::isLegalToPacketizeTogether(SUnit *SUI, SUnit *SUJ) {
// Inline asm cannot go in the packet.
if (I->getOpcode() == Hexagon::INLINEASM)
- assert(0 && "Should not meet inline asm here!");
+ llvm_unreachable("Should not meet inline asm here!");
if (isSoloInstruction(I))
- assert(0 && "Should not meet solo instr here!");
+ llvm_unreachable("Should not meet solo instr here!");
// A save callee-save register function call can only be in a packet
// with instructions that don't write to the callee-save registers.
@@ -3550,8 +3539,7 @@ bool HexagonPacketizerList::isLegalToPacketizeTogether(SUnit *SUI, SUnit *SUJ) {
// isLegalToPruneDependencies
bool HexagonPacketizerList::isLegalToPruneDependencies(SUnit *SUI, SUnit *SUJ) {
MachineInstr *I = SUI->getInstr();
- MachineInstr *J = SUJ->getInstr();
- assert(I && J && "Unable to packetize null instruction!");
+ assert(I && SUJ->getInstr() && "Unable to packetize null instruction!");
const unsigned FrameSize = MF.getFrameInfo()->getStackSize();