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author | Andrew Trick <atrick@apple.com> | 2012-07-07 04:00:00 +0000 |
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committer | Andrew Trick <atrick@apple.com> | 2012-07-07 04:00:00 +0000 |
commit | 2661b411ccc81b1fe19194d3f43b2630cbef3f28 (patch) | |
tree | 0decaebaee6c3a1a9d42df6b5619de1ffb2fac7d /lib/Target/Hexagon | |
parent | 06495cd7f2a91c4f659eac5e55b1c08b014d0a08 (diff) | |
download | llvm-2661b411ccc81b1fe19194d3f43b2630cbef3f28.tar.gz llvm-2661b411ccc81b1fe19194d3f43b2630cbef3f28.tar.bz2 llvm-2661b411ccc81b1fe19194d3f43b2630cbef3f28.tar.xz |
I'm introducing a new machine model to simultaneously allow simple
subtarget CPU descriptions and support new features of
MachineScheduler.
MachineModel has three categories of data:
1) Basic properties for coarse grained instruction cost model.
2) Scheduler Read/Write resources for simple per-opcode and operand cost model (TBD).
3) Instruction itineraties for detailed per-cycle reservation tables.
These will all live side-by-side. Any subtarget can use any
combination of them. Instruction itineraries will not change in the
near term. In the long run, I expect them to only be relevant for
in-order VLIW machines that have complex contraints and require a
precise scheduling/bundling model. Once itineraries are only actively
used by VLIW-ish targets, they could be replaced by something more
appropriate for those targets.
This tablegen backend rewrite sets things up for introducing
MachineModel type #2: per opcode/operand cost model.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159891 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/Hexagon')
-rw-r--r-- | lib/Target/Hexagon/Hexagon.td | 12 | ||||
-rw-r--r-- | lib/Target/Hexagon/HexagonSchedule.td | 5 | ||||
-rw-r--r-- | lib/Target/Hexagon/HexagonScheduleV4.td | 6 |
3 files changed, 14 insertions, 9 deletions
diff --git a/lib/Target/Hexagon/Hexagon.td b/lib/Target/Hexagon/Hexagon.td index 8201de3f2a..451e56206e 100644 --- a/lib/Target/Hexagon/Hexagon.td +++ b/lib/Target/Hexagon/Hexagon.td @@ -47,14 +47,14 @@ def HexagonInstrInfo : InstrInfo; // Hexagon processors supported. //===----------------------------------------------------------------------===// -class Proc<string Name, ProcessorItineraries Itin, +class Proc<string Name, SchedMachineModel Model, list<SubtargetFeature> Features> - : Processor<Name, Itin, Features>; + : ProcessorModel<Name, Model, Features>; -def : Proc<"hexagonv2", HexagonItineraries, [ArchV2]>; -def : Proc<"hexagonv3", HexagonItineraries, [ArchV2, ArchV3]>; -def : Proc<"hexagonv4", HexagonItinerariesV4, [ArchV2, ArchV3, ArchV4]>; -def : Proc<"hexagonv5", HexagonItinerariesV4, [ArchV2, ArchV3, ArchV4, ArchV5]>; +def : Proc<"hexagonv2", HexagonModel, [ArchV2]>; +def : Proc<"hexagonv3", HexagonModel, [ArchV2, ArchV3]>; +def : Proc<"hexagonv4", HexagonModelV4, [ArchV2, ArchV3, ArchV4]>; +def : Proc<"hexagonv5", HexagonModelV4, [ArchV2, ArchV3, ArchV4, ArchV5]>; // Hexagon Uses the MC printer for assembler output, so make sure the TableGen diff --git a/lib/Target/Hexagon/HexagonSchedule.td b/lib/Target/Hexagon/HexagonSchedule.td index b4df6784e7..d1076b8e44 100644 --- a/lib/Target/Hexagon/HexagonSchedule.td +++ b/lib/Target/Hexagon/HexagonSchedule.td @@ -41,9 +41,12 @@ def HexagonItineraries : InstrItinData<SYS , [InstrStage<1, [LSUNIT]>]>, InstrItinData<MARKER , [InstrStage<1, [LUNIT, LSUNIT, MUNIT, SUNIT]>]>, InstrItinData<PSEUDO , [InstrStage<1, [LUNIT, LSUNIT, MUNIT, SUNIT]>]> - ]> { + ]>; + +def HexagonModel : SchedMachineModel { // Max issue per cycle == bundle width. let IssueWidth = 4; + let Itineraries = HexagonItineraries; } //===----------------------------------------------------------------------===// diff --git a/lib/Target/Hexagon/HexagonScheduleV4.td b/lib/Target/Hexagon/HexagonScheduleV4.td index 8d6f7b2b7a..9b41126ca6 100644 --- a/lib/Target/Hexagon/HexagonScheduleV4.td +++ b/lib/Target/Hexagon/HexagonScheduleV4.td @@ -52,12 +52,14 @@ def HexagonItinerariesV4 : InstrItinData<MARKER , [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>]>, InstrItinData<PREFIX , [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>]>, InstrItinData<PSEUDO , [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>]> - ]> { + ]>; + +def HexagonModelV4 : SchedMachineModel { // Max issue per cycle == bundle width. let IssueWidth = 4; + let Itineraries = HexagonItinerariesV4; } - //===----------------------------------------------------------------------===// // Hexagon V4 Resource Definitions - //===----------------------------------------------------------------------===// |