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author | Sergei Larin <slarin@codeaurora.org> | 2012-09-14 15:07:59 +0000 |
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committer | Sergei Larin <slarin@codeaurora.org> | 2012-09-14 15:07:59 +0000 |
commit | c6a6660c6271d3309379ff439f66eb0e6ad48e3a (patch) | |
tree | d267f801d562c3d7b344e011759f5b912b4a3df8 /lib/Target/Hexagon | |
parent | c5252da873d547a19069eaf9030fec203f128f66 (diff) | |
download | llvm-c6a6660c6271d3309379ff439f66eb0e6ad48e3a.tar.gz llvm-c6a6660c6271d3309379ff439f66eb0e6ad48e3a.tar.bz2 llvm-c6a6660c6271d3309379ff439f66eb0e6ad48e3a.tar.xz |
DAG post-process for Hexagon MI scheduler
This patch introduces a possibility for Hexagon MI scheduler
to perform some target specific post- processing on the scheduling
DAG prior to scheduling.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163903 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/Hexagon')
-rw-r--r-- | lib/Target/Hexagon/HexagonMachineScheduler.cpp | 27 | ||||
-rw-r--r-- | lib/Target/Hexagon/HexagonMachineScheduler.h | 7 |
2 files changed, 34 insertions, 0 deletions
diff --git a/lib/Target/Hexagon/HexagonMachineScheduler.cpp b/lib/Target/Hexagon/HexagonMachineScheduler.cpp index 3e4b5b6ecc..1db6f5ee61 100644 --- a/lib/Target/Hexagon/HexagonMachineScheduler.cpp +++ b/lib/Target/Hexagon/HexagonMachineScheduler.cpp @@ -20,6 +20,22 @@ using namespace llvm; +/// Platform specific modifications to DAG. +void VLIWMachineScheduler::postprocessDAG() { + SUnit* LastSequentialCall = NULL; + // Currently we only catch the situation when compare gets scheduled + // before preceding call. + for (unsigned su = 0, e = SUnits.size(); su != e; ++su) { + // Remember the call. + if (SUnits[su].getInstr()->isCall()) + LastSequentialCall = &(SUnits[su]); + // Look for a compare that defines a predicate. + else if (SUnits[su].getInstr()->isCompare() && LastSequentialCall) + SUnits[su].addPred(SDep(LastSequentialCall, SDep::Order, 0, /*Reg=*/0, + false)); + } +} + /// Check if scheduling of this SU is possible /// in the current packet. /// It is _not_ precise (statefull), it is more like @@ -67,6 +83,13 @@ bool VLIWResourceModel::isResourceAvailable(SUnit *SU) { /// Keep track of available resources. bool VLIWResourceModel::reserveResources(SUnit *SU) { bool startNewCycle = false; + // Artificially reset state. + if (!SU) { + ResourcesModel->clearResources(); + Packet.clear(); + TotalPackets++; + return false; + } // If this SU does not fit in the packet // start a new one. if (!isResourceAvailable(SU)) { @@ -128,6 +151,9 @@ void VLIWMachineScheduler::schedule() { buildDAGWithRegPressure(); + // Postprocess the DAG to add platform specific artificial dependencies. + postprocessDAG(); + // To view Height/Depth correctly, they should be accessed at least once. DEBUG(unsigned maxH = 0; for (unsigned su = 0, e = SUnits.size(); su != e; ++su) @@ -354,6 +380,7 @@ SUnit *ConvergingVLIWScheduler::SchedBoundary::pickOnlyChoice() { for (unsigned i = 0; Available.empty(); ++i) { assert(i <= (HazardRec->getMaxLookAhead() + MaxMinLatency) && "permanent hazard"); (void)i; + ResourceModel->reserveResources(0); bumpCycle(); releasePending(); } diff --git a/lib/Target/Hexagon/HexagonMachineScheduler.h b/lib/Target/Hexagon/HexagonMachineScheduler.h index 51829742ff..5b6f226a00 100644 --- a/lib/Target/Hexagon/HexagonMachineScheduler.h +++ b/lib/Target/Hexagon/HexagonMachineScheduler.h @@ -114,6 +114,8 @@ public: /// Schedule - This is called back from ScheduleDAGInstrs::Run() when it's /// time to do some work. virtual void schedule(); + /// Perform platform specific DAG postprocessing. + void postprocessDAG(); }; /// ConvergingVLIWScheduler shrinks the unscheduled zone using heuristics @@ -222,6 +224,11 @@ public: virtual void releaseBottomNode(SUnit *SU); + unsigned ReportPackets() { + return Top.ResourceModel->getTotalPackets() + + Bot.ResourceModel->getTotalPackets(); + } + protected: SUnit *pickNodeBidrectional(bool &IsTopNode); |