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| author | Rafael Espindola <rafael.espindola@gmail.com> | 2013-12-02 04:55:42 +0000 |
|---|---|---|
| committer | Rafael Espindola <rafael.espindola@gmail.com> | 2013-12-02 04:55:42 +0000 |
| commit | 4a6855441c82b96a57fbfcdf41f8fef591c1cc62 (patch) | |
| tree | b50f420d135709fd98a84603ce9a8933ffef4468 /lib/Target/Hexagon | |
| parent | 5c2a1a302fae0ec99013c82149ef1584090821be (diff) | |
| download | llvm-4a6855441c82b96a57fbfcdf41f8fef591c1cc62.tar.gz llvm-4a6855441c82b96a57fbfcdf41f8fef591c1cc62.tar.bz2 llvm-4a6855441c82b96a57fbfcdf41f8fef591c1cc62.tar.xz | |
Change the default of AsmWriterClassName and isMCAsmWriter.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@196065 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/Hexagon')
| -rw-r--r-- | lib/Target/Hexagon/Hexagon.td | 10 |
1 files changed, 0 insertions, 10 deletions
diff --git a/lib/Target/Hexagon/Hexagon.td b/lib/Target/Hexagon/Hexagon.td index 568798c3a4..c1b6d45ce8 100644 --- a/lib/Target/Hexagon/Hexagon.td +++ b/lib/Target/Hexagon/Hexagon.td @@ -205,14 +205,6 @@ def : Proc<"hexagonv3", HexagonModel, [ArchV2, ArchV3]>; def : Proc<"hexagonv4", HexagonModelV4, [ArchV2, ArchV3, ArchV4]>; def : Proc<"hexagonv5", HexagonModelV4, [ArchV2, ArchV3, ArchV4, ArchV5]>; - -// Hexagon Uses the MC printer for assembler output, so make sure the TableGen -// AsmWriter bits get associated with the correct class. -def HexagonAsmWriter : AsmWriter { - string AsmWriterClassName = "InstPrinter"; - bit isMCAsmWriter = 1; -} - //===----------------------------------------------------------------------===// // Declare the target which we are implementing //===----------------------------------------------------------------------===// @@ -220,6 +212,4 @@ def HexagonAsmWriter : AsmWriter { def Hexagon : Target { // Pull in Instruction Info: let InstructionSet = HexagonInstrInfo; - - let AssemblyWriters = [HexagonAsmWriter]; } |