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| author | Andrew Trick <atrick@apple.com> | 2012-11-06 03:13:46 +0000 |
|---|---|---|
| committer | Andrew Trick <atrick@apple.com> | 2012-11-06 03:13:46 +0000 |
| commit | a78d3228e8b2a14915ea9908dbaaf2c934803e11 (patch) | |
| tree | a38f289fcd4d8cbb94ba239ed6398803d89f81e9 /lib/Target/Hexagon | |
| parent | 887c1fe7010d6f487ce246df6e2fc18eeb4eaa05 (diff) | |
| download | llvm-a78d3228e8b2a14915ea9908dbaaf2c934803e11.tar.gz llvm-a78d3228e8b2a14915ea9908dbaaf2c934803e11.tar.bz2 llvm-a78d3228e8b2a14915ea9908dbaaf2c934803e11.tar.xz | |
ScheduleDAG interface. Added OrderKind to distinguish nonregister dependencies.
This is in preparation for adding "weak" DAG edges, but generally
simplifies the design.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167435 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/Hexagon')
| -rw-r--r-- | lib/Target/Hexagon/HexagonMachineScheduler.cpp | 3 |
1 files changed, 1 insertions, 2 deletions
diff --git a/lib/Target/Hexagon/HexagonMachineScheduler.cpp b/lib/Target/Hexagon/HexagonMachineScheduler.cpp index ca52570358..0e9ef4838d 100644 --- a/lib/Target/Hexagon/HexagonMachineScheduler.cpp +++ b/lib/Target/Hexagon/HexagonMachineScheduler.cpp @@ -31,8 +31,7 @@ void VLIWMachineScheduler::postprocessDAG() { LastSequentialCall = &(SUnits[su]); // Look for a compare that defines a predicate. else if (SUnits[su].getInstr()->isCompare() && LastSequentialCall) - SUnits[su].addPred(SDep(LastSequentialCall, SDep::Order, 0, /*Reg=*/0, - false)); + SUnits[su].addPred(SDep(LastSequentialCall, SDep::Barrier)); } } |