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author | Wesley Peck <peckw@wesleypeck.com> | 2010-02-23 19:15:24 +0000 |
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committer | Wesley Peck <peckw@wesleypeck.com> | 2010-02-23 19:15:24 +0000 |
commit | a70f28ce7dc85d0075a7d86da5d7987b6e306bc6 (patch) | |
tree | fe6fdbcfb4cb0969874e482a41654e709108ef40 /lib/Target/MBlaze/MBlaze.td | |
parent | 2cce3712fafb2e72e144414377cd48f5ab95a5ae (diff) | |
download | llvm-a70f28ce7dc85d0075a7d86da5d7987b6e306bc6.tar.gz llvm-a70f28ce7dc85d0075a7d86da5d7987b6e306bc6.tar.bz2 llvm-a70f28ce7dc85d0075a7d86da5d7987b6e306bc6.tar.xz |
Adding the MicroBlaze backend.
The MicroBlaze is a highly configurable 32-bit soft-microprocessor for
use on Xilinx FPGAs. For more information see:
http://www.xilinx.com/tools/microblaze.htm
http://en.wikipedia.org/wiki/MicroBlaze
The current LLVM MicroBlaze backend generates assembly which can be
compiled using the an appropriate binutils assembler.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@96969 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/MBlaze/MBlaze.td')
-rw-r--r-- | lib/Target/MBlaze/MBlaze.td | 85 |
1 files changed, 85 insertions, 0 deletions
diff --git a/lib/Target/MBlaze/MBlaze.td b/lib/Target/MBlaze/MBlaze.td new file mode 100644 index 0000000000..16797529cb --- /dev/null +++ b/lib/Target/MBlaze/MBlaze.td @@ -0,0 +1,85 @@ +//===- MBlaze.td - Describe the MBlaze Target Machine -----------*- C++ -*-===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +// This is the top level entry point for the MBlaze target. +//===----------------------------------------------------------------------===// + +//===----------------------------------------------------------------------===// +// Target-independent interfaces +//===----------------------------------------------------------------------===// + +include "llvm/Target/Target.td" + +//===----------------------------------------------------------------------===// +// Register File, Calling Conv, Instruction Descriptions +//===----------------------------------------------------------------------===// + +include "MBlazeRegisterInfo.td" +include "MBlazeSchedule.td" +include "MBlazeIntrinsics.td" +include "MBlazeInstrInfo.td" +include "MBlazeCallingConv.td" + +def MBlazeInstrInfo : InstrInfo { + let TSFlagsFields = []; + let TSFlagsShifts = []; +} + + +//===----------------------------------------------------------------------===// +// Microblaze Subtarget features // +//===----------------------------------------------------------------------===// + +def FeaturePipe3 : SubtargetFeature<"pipe3", "HasPipe3", "true", + "Implements 3-stage pipeline.">; +def FeatureBarrel : SubtargetFeature<"barrel", "HasBarrel", "true", + "Implements barrel shifter.">; +def FeatureDiv : SubtargetFeature<"div", "HasDiv", "true", + "Implements hardware divider.">; +def FeatureMul : SubtargetFeature<"mul", "HasMul", "true", + "Implements hardware multiplier.">; +def FeatureFSL : SubtargetFeature<"fsl", "HasFSL", "true", + "Implements FSL instructions.">; +def FeatureEFSL : SubtargetFeature<"efsl", "HasEFSL", "true", + "Implements extended FSL instructions.">; +def FeatureMSRSet : SubtargetFeature<"msrset", "HasMSRSet", "true", + "Implements MSR register set and clear.">; +def FeatureException : SubtargetFeature<"exception", "HasException", "true", + "Implements hardware exception support.">; +def FeaturePatCmp : SubtargetFeature<"patcmp", "HasPatCmp", "true", + "Implements pattern compare instruction.">; +def FeatureFPU : SubtargetFeature<"fpu", "HasFPU", "true", + "Implements floating point unit.">; +def FeatureESR : SubtargetFeature<"esr", "HasESR", "true", + "Implements ESR and EAR registers">; +def FeaturePVR : SubtargetFeature<"pvr", "HasPVR", "true", + "Implements processor version register.">; +def FeatureMul64 : SubtargetFeature<"mul64", "HasMul64", "true", + "Implements multiplier with 64-bit result">; +def FeatureSqrt : SubtargetFeature<"sqrt", "HasSqrt", "true", + "Implements sqrt and floating point convert.">; +def FeatureMMU : SubtargetFeature<"mmu", "HasMMU", "true", + "Implements memory management unit.">; + +//===----------------------------------------------------------------------===// +// MBlaze processors supported. +//===----------------------------------------------------------------------===// + +class Proc<string Name, list<SubtargetFeature> Features> + : Processor<Name, MBlazeGenericItineraries, Features>; + + +def : Proc<"v400", []>; +def : Proc<"v500", []>; +def : Proc<"v600", []>; +def : Proc<"v700", []>; +def : Proc<"v710", []>; + +def MBlaze : Target { + let InstructionSet = MBlazeInstrInfo; +} |