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| author | Anton Korobeynikov <asl@math.spbu.ru> | 2009-10-10 22:17:47 +0000 |
|---|---|---|
| committer | Anton Korobeynikov <asl@math.spbu.ru> | 2009-10-10 22:17:47 +0000 |
| commit | 8f8e9f08300f62db802767c9fb23b40aab66e51e (patch) | |
| tree | b078619524192d45acefb26c1e7abfdb9465a3e2 /lib/Target/MSP430/MSP430InstrInfo.td | |
| parent | 558c36729f8fb6606f06d034c5be6c83e4f4b509 (diff) | |
| download | llvm-8f8e9f08300f62db802767c9fb23b40aab66e51e.tar.gz llvm-8f8e9f08300f62db802767c9fb23b40aab66e51e.tar.bz2 llvm-8f8e9f08300f62db802767c9fb23b40aab66e51e.tar.xz | |
It seems that OR operation does not affect status reg at all.
Remove impdef of SRW. This fixes PR4779
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83739 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/MSP430/MSP430InstrInfo.td')
| -rw-r--r-- | lib/Target/MSP430/MSP430InstrInfo.td | 20 |
1 files changed, 8 insertions, 12 deletions
diff --git a/lib/Target/MSP430/MSP430InstrInfo.td b/lib/Target/MSP430/MSP430InstrInfo.td index b5f9491b45..ced612e863 100644 --- a/lib/Target/MSP430/MSP430InstrInfo.td +++ b/lib/Target/MSP430/MSP430InstrInfo.td @@ -671,30 +671,26 @@ def OR16rm : Pseudo<(outs GR16:$dst), (ins GR16:$src1, memsrc:$src2), let isTwoAddress = 0 in { def OR8mr : Pseudo<(outs), (ins memdst:$dst, GR8:$src), "bis.b\t{$src, $dst}", - [(store (or (load addr:$dst), GR8:$src), addr:$dst), - (implicit SRW)]>; + [(store (or (load addr:$dst), GR8:$src), addr:$dst)]>; def OR16mr : Pseudo<(outs), (ins memdst:$dst, GR16:$src), "bis.w\t{$src, $dst}", - [(store (or (load addr:$dst), GR16:$src), addr:$dst), - (implicit SRW)]>; + [(store (or (load addr:$dst), GR16:$src), addr:$dst)]>; def OR8mi : Pseudo<(outs), (ins memdst:$dst, i8imm:$src), "bis.b\t{$src, $dst}", - [(store (or (load addr:$dst), (i8 imm:$src)), addr:$dst), - (implicit SRW)]>; + [(store (or (load addr:$dst), (i8 imm:$src)), addr:$dst)]>; def OR16mi : Pseudo<(outs), (ins memdst:$dst, i16imm:$src), "bis.w\t{$src, $dst}", - [(store (or (load addr:$dst), (i16 imm:$src)), addr:$dst), - (implicit SRW)]>; + [(store (or (load addr:$dst), (i16 imm:$src)), addr:$dst)]>; def OR8mm : Pseudo<(outs), (ins memdst:$dst, memsrc:$src), "bis.b\t{$src, $dst}", - [(store (or (load addr:$dst), (i8 (load addr:$src))), addr:$dst), - (implicit SRW)]>; + [(store (or (i8 (load addr:$dst)), + (i8 (load addr:$src))), addr:$dst)]>; def OR16mm : Pseudo<(outs), (ins memdst:$dst, memsrc:$src), "bis.w\t{$src, $dst}", - [(store (or (load addr:$dst), (i16 (load addr:$src))), addr:$dst), - (implicit SRW)]>; + [(store (or (i16 (load addr:$dst)), + (i16 (load addr:$src))), addr:$dst)]>; } } // isTwoAddress = 1 |