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| author | Jakob Stoklund Olesen <stoklund@2pi.dk> | 2010-05-24 21:46:58 +0000 |
|---|---|---|
| committer | Jakob Stoklund Olesen <stoklund@2pi.dk> | 2010-05-24 21:46:58 +0000 |
| commit | 09bc0298650c76db1a06e20ca84c1dcb34071600 (patch) | |
| tree | 6fb4e150957445020262c64bacf93e4a91b5705a /lib/Target/MSP430/MSP430RegisterInfo.td | |
| parent | 3946043a80a043b3cf43b34bf068feaadc46485b (diff) | |
| download | llvm-09bc0298650c76db1a06e20ca84c1dcb34071600.tar.gz llvm-09bc0298650c76db1a06e20ca84c1dcb34071600.tar.bz2 llvm-09bc0298650c76db1a06e20ca84c1dcb34071600.tar.xz | |
Replace the tablegen RegisterClass field SubRegClassList with an alist-like data
structure that represents a mapping without any dependencies on SubRegIndex
numbering.
This brings us closer to being able to remove the explicit SubRegIndex
numbering, and it is now possible to specify any mapping without inventing
*_INVALID register classes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104563 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/MSP430/MSP430RegisterInfo.td')
| -rw-r--r-- | lib/Target/MSP430/MSP430RegisterInfo.td | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/lib/Target/MSP430/MSP430RegisterInfo.td b/lib/Target/MSP430/MSP430RegisterInfo.td index db3f0e789a..bacc1c0506 100644 --- a/lib/Target/MSP430/MSP430RegisterInfo.td +++ b/lib/Target/MSP430/MSP430RegisterInfo.td @@ -104,7 +104,7 @@ def GR16 : RegisterClass<"MSP430", [i16], 16, // Volatile, but not allocable PCW, SPW, SRW, CGW]> { - let SubRegClassList = [GR8]; + let SubRegClasses = [(GR8 subreg_8bit)]; let MethodProtos = [{ iterator allocation_order_end(const MachineFunction &MF) const; }]; |