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| author | Ahmed Bougacha <ahmed.bougacha@gmail.com> | 2013-05-31 23:45:26 +0000 |
|---|---|---|
| committer | Ahmed Bougacha <ahmed.bougacha@gmail.com> | 2013-05-31 23:45:26 +0000 |
| commit | 23ed37a6b76e79272194fb46597f7280661b828f (patch) | |
| tree | a2c447458a013a1f1bcbdc84d43fe3c55c416a0d /lib/Target/MSP430/MSP430RegisterInfo.td | |
| parent | cd8e3c4dcf4383b8b1c16827c6326f6e9bc49d51 (diff) | |
| download | llvm-23ed37a6b76e79272194fb46597f7280661b828f.tar.gz llvm-23ed37a6b76e79272194fb46597f7280661b828f.tar.bz2 llvm-23ed37a6b76e79272194fb46597f7280661b828f.tar.xz | |
Make SubRegIndex size mandatory, following r183020.
This also makes TableGen able to compute sizes/offsets of synthesized
indices representing tuples.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183061 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/MSP430/MSP430RegisterInfo.td')
| -rw-r--r-- | lib/Target/MSP430/MSP430RegisterInfo.td | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/lib/Target/MSP430/MSP430RegisterInfo.td b/lib/Target/MSP430/MSP430RegisterInfo.td index 07619d0675..4010781a86 100644 --- a/lib/Target/MSP430/MSP430RegisterInfo.td +++ b/lib/Target/MSP430/MSP430RegisterInfo.td @@ -43,7 +43,7 @@ def R13B : MSP430Reg<13, "r13">; def R14B : MSP430Reg<14, "r14">; def R15B : MSP430Reg<15, "r15">; -def subreg_8bit : SubRegIndex { let Namespace = "MSP430"; } +def subreg_8bit : SubRegIndex<8> { let Namespace = "MSP430"; } let SubRegIndices = [subreg_8bit] in { def PCW : MSP430RegWithSubregs<0, "r0", [PCB]>; |